• 대한전자공학회논문지SD
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• 제45권2호
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• pp.125-129
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• 2008

본 논문에서는 Q값(Q-factor)을 증가시킬 수 있는 저전압 능동(active) CMOS 인덕터를 제안하고 설계하였다. Q값을 증가시키기 위한 방법으로 저전압 능동 CMOS 인덕터에 피드백 저항을 삽입하여 등가적인 인덕턴스와 Q값을 증가시켰다. 저전압 능동 CMOS 인덕터는 0.18um 표준 CMOS 공정으로 설계하였으며 모의실험은 애질런트사의 ADS 시뮬레이터를 이용하였다. 모의 실험결과 설계된 피드백 저항을 삽입한 저전압 능동 CMOS 인덕터는 4GHz에서 1.5nH의 인덕턴스와 최대 3000이상의 Q값을 가졌고 소비전력은 5.4mW였다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 추계종합학술대회
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• pp.873-876
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• 2005

본 논문은 광대역 CMOS 연상증폭기를 위한 새로운 전류 전이 검사 기술을 제안한다. 본 검사 방법에서는 결함이 있는 연산증폭기와 결함이 없는 연산 증폭기를 자동적으로 구별해 내기 위해 증폭기의 공급 전원으로부터 순간적으로 변하는 전류와 출력응답을 측정한다. 광대역 CMOS 연산증폭기는 0.25${\mu}$m CMOS 공정을 이용하여 설계되었다. 이 검사 기술은 CMOS 연산증폭기내에서 발생한 거폭결함 (catastrophic faults)을 검출하고 분석할 수 있으며, 검사비용이 저렴하고 측정방법이 간단하다.

• 한국통신학회논문지
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• 제18권4호
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• pp.602-610
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• 1993

새로운 능동 소자인 DDA와 이를 이용한 차동적분기를 설계하였다. DDA는 기존의 OP-AMP로 구성된 응용 회로의 설계시 외부 소자의 정합 문제를 개선할 수 있다는 장점을 갖는다. DDA의 설계는 트랜스컨덕턴스 소자인 differential pair를 이용하여 $2{\mu}m$ 설계 규칙에 맞게 하였다. 이 DDA의 성능을 평가하기 위하여 전압 인버터와 레벨 쉬프터로 구성하여 특성을 고찰한 결과 우수함을 입증하였다. 그리고 CMOS DDA를 이용하여 접지 저항의 모의와 차동적분기를 설계하였고, DDA 차동적분기의 특성이 OP-AMP 차동적분기의 특성을 일치함을 알 수 있었다. 또한 설계된 CMOS DDA와 DDA 차동적분기를 MOSIS $2{\mu}m$ CMOS 공정 기술을 적용하여 layout 하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.180-183
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• 2000

Beginning with a brief introduction on near 100 nm or below CMOS devices, this paper addresses novel devices for future sub-100 nm CMOS. First, key issues such as gate materials, gate dielectric, source/drain, and channel in Si bulk CMOS devices are considered. CMOS devices with different channel doping and structure are introduced by explaining a figure of merit. Finally, novel device structures such as SOI, SiGe, and double-gate devices will be discussed for possible candidates for sub-100 nm CMOS.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.467-468
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• 2008

In this paper, a logic family, the transmission gate CMOS(TG CMOS) is proposed, which combines the transmission gate and pass transistor resulting in a different configuration from traditional full CMOS. In the simulation, basic cells comprising this logic are designed and their dynamic responses are analyzed. The simulation shows their performance is exceeding that of conventional full CMOS.

• 전기학회논문지
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• 제57권10호
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• pp.1888-1892
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• 2008

In this paper, a new parallel CMOS self-bias differential amplifier is designed to use in high-speed analog signal processing circuits. The designed parallel CMOS self-bias differential amplifier is developed by using internal biasing circuits and the complement gain stages which are parallel connected. And also, the parallel architecture of the designed parallel CMOS self-bias differential amplifier can improve the gain and gain-bandwidth product of the typical CMOS self-bias differential amplifier. With 1.8V $0.8{\mu}m$ CMOS process parameter, the results of HSPICE show that the designed parallel CMOS self-bias differential amplifier has a dc gain and a gain-bandwidth product of 64 dB and 49 MHz respectively.

• 전자공학회논문지A
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• 제31A권10호
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• 전자공학회논문지A
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• 제33A권2호
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• pp.184-195
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• 1996

Beause BiCMOS logic circuits consist of CMOS part which constructs logic function and bipolar part which drives output load, the effect of short faults on BiCMOS logic circuits represented different types from that on CMOS. This paper proposes new test method which detects short faults on BiCMOS logic circuits using current path graph. Proposed method transforms BiCMOS circuits into raph constructed by nodes and edges using extended switch-level model and separates the transformed graph into pull-up part and pull-down part. Also, proposed method eliminates edge or add new edge, according ot short faults on terminals of transistor, and can detect short faults using current path graph that generated from on- or off-relations of transistor by input patterns. Properness of proposed method is verified by comparing it with results of spice simulation.

• 전자공학회논문지A
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• 제32A권12호
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• pp.198-208
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• 1995

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

• E2M - 전기 전자와 첨단 소재
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• 제8권2호
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• pp.204-210
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• 1995

The characteristics of the internal circuits and the load capacitance should be included to optimize the size of BiCMOS buffer. In order to get the optimum size and delay time of the BiCMOS buffer, new size plane is suggested. By using the size plane, the optimum characteristics of CMOS buffer according to the number of stages can be obtained. From this method, delaytime, .tau.$_{D}$, is obtained 2.39 nsec with $V_{\var}$=5V, $C_{L}$=5pF, W=30.mu.m and $A_{e}$=135.mu. $m^{2}$.>..>...>.