• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.33-37
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• 2007

This paper presents the implementation technique to reduce circuit area occupation in designing Low Noise Amplifier (LNA) using vertical shunt symmetric inductor. We applied a vertical shunt symmetric inductor to match the input and output in 3 GHz CMOS LNA to reduce the circuit area. This size efficient amplifier has been designed in a $0.18\;{\mu}m$ digital logic CMOS process. In this paper, the case of conventional asymmetric inductor, and vertical shunt symmetrical inductor with a relatively higher number of turns have been compared in order to efficient a size efficient CMOS LNA design method while still retaining the circuit operation characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.439-440
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• 2018

본 논문에서는 차량용 레이더를 위한 저 위상잡음 24GHz CMOS 전압제어발진기를 제안한다. 이러한 회로는 1.8볼트 전원에서 동작하며, 낮은 위상잡음을 가지도록 설계되어 있다. 제안한 회로는 TSMC $0.13{\mu}m$ 고주파 CMOS 공정으로 구현되어 있다. 제안한 회로는 최근 발표된 연구결과에 비해 저 전력동작에서 저 위상잡음 및 낮은 잡음지수 특성을 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.753-754
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• 2014

본 논문에서는 차량 충돌 예방 장거리 레이더용 고 이득 및 저 잡음 77GHz CMOS 저 잡음 증폭기를 제안한다. 이러한 회로는 2볼트 전원전압 및 77GHz의 주파수에서 동작한다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 전체 칩 면적을 줄이기 위해 실제 수동형 인덕터 대신 전송선을 이용하였다. 제안한 회로는 최근 발표된 연구결과에 비해 34.33dB의 가장 높은 전압이득과 5.6dB의 가장 낮은 잡음지수 특성을 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.647-648
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• 2016

본 논문에서는 차량용 레이더를 위한 저 전력 24GHz CMOS 저 잡음 증폭기를 제안한다. 이러한 회로는 1.8볼트 전원에서 동작하며, 저 전력에서도 높은 전압 이득과 낮은 잡음지수를 가지도록 설계되어 있다. 제안한 회로는 TSMC $0.13{\mu}m$ 고주파 CMOS 공정으로 구현되어 있다. 제안한 회로는 최근 발표된 연구결과에 비해 저 전력동작에서 높은 전압이득 및 낮은 잡음지수 특성을 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.467-468
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• 2019

본 논문은 차량용 장거리 레이더를 위한 저 위상잡음 77GHz CMOS 전압제어발진기를 제안한다. 이러한 회로는 낮은 위상잡음을 가지도록 설계되어 있고, 1.5볼트 전원에서 동작한다. 제안한 회로는 TSMC $0.13{\mu}m$ 고주파 CMOS 공정으로 설계하였다. 제안한 회로는 최근 발표된 연구결과에 비해 저 위상잡음, 저 전력 및 적은 면적 특성을 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.569-572
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• 2014

This paper presents a CMOS switched-capacitor interface circuit for MEMS capacitive sensors. It consist of a capacitance to voltage converter(CVC), a second-order ${\Sigma}{\Delta}$ modulator, and a comparator. A bias circuit is also designed to supply constant bias voltages and currents. This circuit employes the correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques to reduce low-frequency noise and offset. The designed CVC has a sensitivity of 20.53mV/fF and linearity errors less than 0.036%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 5% as the input voltage amplitude increases by 100mV. The designed interface circuit shows linearity errors less than 0.13%, and the current consumption is 0.73mA. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V. The size of the designed chip including PADs is $1117um{\times}983um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.267-270
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• 2014

This paper presents a CMOS interface circuit for vibration energy harvesting. The proposed circuit consists of an AC-DC converter and a DC-DC boost converter. The AC-DC converter rectifies the AC signals from vibration devices(PZT), and the DC-DC boost converter generates a boosted and regulated output at a predefined level. A full-wave rectifier using active diodes is used as the AC-DC converter for high efficiency, and a schottky diode type DC-DC boost converter is used for a simple control circuitry. A MPPT(Maximum Power Point Tracking) control is also employed to harvest the maximum power from the PZT. The proposed circuit has been designed in a 0.35um CMOS process. The chip area is $530um{\times}325um$. Simulation results shows that the maximum efficiencies of the AC-DC converter and DC-DC boost converter are 97.7% and 89.2%, respectively. The maximum efficiency of the entire system is 87.2%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.917-922
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• 2010

In this paper, a new temperature-insensitive CMOS dual-mode current reference for low-voltage low-power mixed-mode circuits is proposed. The temperature independent reference current is generated by summing a proportional to absolute temperature(PTAT) current and a complementary to absolute temperature(CTAT) current. The temperature insensitivity was achieved by the mobility and the other which is inversely proportional to mobility. As the results, the temperature dependency of output currents was measured to be $0.38{\mu}A/^{\circ}C$ and $0.39{\mu}A/^{\circ}C$, respectively. And also, the power dissipation is 0.84mW on 2V voltage supply. These results are verified by the $0.18{\mu}m$ n-well CMOS parameter.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.55-60
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• 1984

With the advancement of CMOS technology, it has become attractive to employ complex gate structures in realizing digital circuits. A new test generation algorithm for CMOS complex gates to detect all stuck-open and stuck-on faults considering internal gate response and unknown state is proposed. Minimal and complete set can be derived by this algorithm. Also, it is verified that such a test set is generated applying this algorithm to arbitrary CMOS complex gates by computer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.974-984
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• 2000

A CMOS voltage driver circuit for voltage down converter is proposed. An adaptive biasing technique is used to enhance load regulation characteristics. The proposed driver circuit uses the NMOS transistor as a driving transistor, so it does not suffer from large Miller capacitances which is one of the problems with conventional PMOS driving transistor, and hence achieves good phase margin and stable frequency response. No additional complex circuit for frequency compensation such as compensation capacitor is required in this implementation. For the same current capability, the size of NMOS transistor in driver circuit is smaller than that of PMOS counterpart. So the smaller die area can be achieved. The circuits is implemented using a 0.8 ${\mu}{\textrm}{m}$ CMOS process and has a die area of 150 ${\mu}{\textrm}{m}$ x 360 ${\mu}{\textrm}{m}$. Proposed circuit has a quiescent power of 60 . In the current driving range from 100 $mutextrm{A}$ to 50 ㎃, load regulation of 5.6 ㎷ is measured.