• 한국전자통신학회논문지
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• 제13권5호
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• pp.949-958
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• 2018

음성 인식 제어 시스템은 사용자의 음성을 인식하여 주변 장치를 제어하는 시스템이다. 최근 음성 인식 제어 시스템은 스마트기기 뿐만 아니라, IoT(: Internet of Things), 로봇, 차량에 이르기까지 다양한 환경에 적용되고 있다. 이러한 음성 인식 제어 시스템은 사용자의 음성 외에 주변 잡음에 의한 인식률 저하가 발생한다. 이에 본 논문은 사용자의 음성 외에 주변 잡음을 제거하기 위하여 MEMS(: Microelectromechanical Systems) 마이크로폰용 이중 채널 음성 빔포밍 하드웨어 구조를 제안하였으며, 제안한 하드웨어 구조를 TowerJazz $0.18{\mu}m$ CMOS(: Complementary Metal-Oxide Semiconductor) 공정을 이용하여 ASIC(: Application-Specific Integrated Circuit)을 설계하였다. 설계한 이중 채널 음성 빔포밍 ASIC은 $48mm^2$의 Die size를 가지며, 사용자의 음성에 대한 지향성 특성을 측정한 결과 4.233㏈의 특성을 보였다.

• Transactions on Electrical and Electronic Materials
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• 제12권6호
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• pp.262-266
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• 2011

A simulation study of a current-mode direct current (DC)-DC boost converter is presented in this paper. This converter, with a fully-integrated power module, is implemented by using bipolar complementary metal-oxide semiconductor (BiCMOS) technology. The current-sensing circuit has an op-amp to achieve high accuracy. With the sense metal-oxide semiconductor field-effect transistor (MOSFET) in the current sensor, the sensed inductor current with the internal ramp signal can be used for feedback control. In addition, BiCMOS technology is applied to the converter, for accurate current sensing and low power consumption. The DC-DC converter is designed with a standard 0.35 ${\mu}m$ BiCMOS process. The off-chip inductor-capacitor (LC) filter is operated with an inductance of 1 mH and a capacitance of 12.5 nF. Simulation results show the high performance of the current-sensing circuit and the validity of the BiCMOS converter. The output voltage is found to be 4.1 V with a ripple ratio of 1.5% at the duty ratio of 0.3. The sensing current is measured to be within 1 mA and follows to fit the order of the aspect ratio, between sensing and power FET.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.118-119
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• 2007

High performance three-dimensional (3-D) stacked poly-Si complementary metal-oxide semiconductor (CMOS) inverters with a high quality laser crystallized channel were fabricated. Low temperature crystallization methods of a-Si film using the excimer-laser annealing (ELA) and sequential lateral solidification (SLS) were performed. The NMOS thin-film-transistor (TFT) at lower layer of CMOS was fabricated on oxidized bulk Si substrate, and the PMOS TFT at upper layer of CMOS was fabricated on interlayer dielectric film. The 3-D stacked poly-Si CMOS inverter showed excellent electrical characteristics and was enough for the vertical integrated CMOS applications.

• 센서학회지
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• 제30권4호
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• pp.236-242
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• 2021

In this paper, we report the fabrication of the tip-on-gate of a field-effect-transistor (ToGoFET) probe using a standard complementary metal-oxide-semiconductor (CMOS) process and the performance evaluation of the fabricated probe. After the CMOS process, I-V characteristic measurement was performed on the reference MOSFET. We confirmed that the ToGoFET probe could be operated at a gate voltage of 0 V due to channel ion implantation. The transconductance at the operating point (Vg = 0 V, Vd = 2 V) was 360 ㎂/V. After the fabrication process was completed, calibration was performed using a pure metal sample. For sensitivity calibration, the relationship between the input voltage of the sample and the output current of the probe was determined and the result was consistent with the measurement result of the reference MOSFET. An oxide sample measurement was performed as an example of an application of the new ToGoFET probe. According to the measurement, the ToGoFET probe could spatially resolve a hundred nanometers with a height of a few nanometers in both the topographic image and the ToGoFET image.

• 센서학회지
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• 제31권1호
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• pp.1-5
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• 2022

In this paper, the photocurrent characteristics of gate/body-tied (GBT) metal-oxide semiconductor field-effect transistor (MOSFET)-type photodetector with high sensitivity in the 408 nm - 941 nm range are presented. High sensitivity is important for photodetectors, which are used in several scientific and industrial applications. Owing to its inherent amplifying characteristics, the GBT MOSFET-type photodetector exhibits high sensitivity. The presented GBT MOSFET-type photodetector was designed and fabricated via a standard 0.18 ㎛ complementary metal-oxide-semiconductor (CMOS) process, and its characteristics were analyzed. The photodetector was analyzed with respect to its width to length (W/L) ratio, bias voltage, and incident-light wavelength. It was confirmed experimentally that the presented GBT MOSFET-type photodetector has over 100 times higher sensitivity than a PN-junction photodiode with the same area in the 408 nm - 941 nm range.

• 센서학회지
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• 제31권1호
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• pp.12-15
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• 2022

In this study, we studied the effects of transfer gate on the photocurrent characteristics of gate/body-tied (GBT) metal-oxide semiconductor field-effect transistor (MOSFET)-type photodetector. The GBT MOSFET-type photodetector has high sensitivity owing to the amplifying characteristic of the photocurrent generated by light. The transfer gate controls the flow of photocurrent by controlling the barrier to holes, thereby varying the sensitivity of the photodetector. The presented GBT MOSFET-type photodetector using a built-in transfer gate was designed and fabricated via a 0.18-㎛ standard complementary metal-oxide-semiconductor (CMOS) process. Using a laser diode, the photocurrent was measured according to the wavelength of the incident light by adjusting the voltage of the transfer gate. Variable sensitivity of the presented GBT MOSFET-type photodetector was experimentally confirmed by adjusting the transfer gate voltage in the range of 405 nm to 980 nm.

• 반도체디스플레이기술학회지
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• 제9권2호
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• pp.7-10
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• 2010

In this paper, we design a modem SoC (System on Chip) for low power consumption and high speed wireless communications. Among various schemes of high speed communications, an MB-OFDM (Multi Band-Orthogonal Frequency Division Multiplexing) UWB (Ultra-Wide-Band) chip is designed. The MB-OFDM uses wide-band frequency to provide high speed data rate. Additionally, the system imposes no interference to other services. The 90nm CMOS (Complementary Metal-Oxide Semiconductor) technology is used for the SoC design. Especially, power management mode is implemented to reduce the power consumption.

• Journal of the Optical Society of Korea
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• 제15권1호
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• pp.1-3
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• 2011

We characterize and analyze silicon avalanche photodetectors (APDs) fabricated with standard complementary metal-oxide-semiconductor (CMOS) technology. Current characteristics, responsivity, avalanche gain, and photodetection bandwidth of CMOS-APDs based on two types of PN junctions, N-well/P-substrate and $P^+$/N-well junctions, are compared and analyzed. It is demonstrated that the CMOS-APD using the $P^+$/N-well junction has higher responsivity as well as higher photodetection bandwidth than N-well/P-substrate. In addition, the important factors influencing CMOS-APD performance are clarified from this investigation.

• 한국통신학회논문지
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• 제34권8C호
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• pp.806-813
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• 2009

본 논문은 고속 무선 통신을 위한 모뎀 설계에 관한 것이다. 고속 통신을 위한 기술에는 여러 가지가 있는데, 그 중 넓은 주파수를 사용하고 여타 서비스에 주파수 간섭을 일으키지 않는 기술인 MB-OFDM (Multi-Band Orthogonal Frequency Division Multiplexing) 방식의 UWB (Ultra-Wideband) 모뎀의 SoC (System-on-Chip) 칩을 설계하였다. 개발된 모뎀 SoC 칩의 기저대역 시스템은 WiMedia에서 정의한 표준안을 따라서 설계되었다. 설계된 SoC 칩은 코어 부분인 FFT/lFFT (Fast Fourier Transform/lnverse Fast Fourier Transform), 송신부, 심볼동기 및 주파수 오프셋 추정부, 비터비 디코더, 그리고 기타 수신부등으로 구성되어 있다. 반도체 공정은 90nm CMOS (Complementary Metal-Oxide-Semiconductor) 공정을 사용하였고, 칩 사이즈는 약 5mm x 5mm 이다. 2009년 7월 20일에 fab-out되었다.

• 한국산학기술학회논문지
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• 제9권2호
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• pp.462-469
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• 2008

본 논문에서는 KOINONIA 무선 개인 영역 네트워크 (WPAN: Wireless Personal Area Network) 표준을 프로그래밍 가능한 게이트 배열 (FPGA: Field-Programmable Gate Array)로 설계하고 시스템 온 칩 (SoC: System on Chip)으로 구현하였다. 변조부에서는 정진폭을 유지할 수 있도록 잉여 비트를 이용하여 부호화하였고, 수신부에서는 이 잉여 비트를 복호 하는데 사용함으로써 낮은 신호 대 잡음비 (SNR: Signal to Noise Ratio)에서도 동작이 가능하게 하였다. KOINONIA WPAN은 400만 게이트 급의 FPGA에서 44MHz이상으로 동작하였으며, 무선 주파수 (RF: Radio Frequency) 모듈과의 연동 실험에서는 최소 입력 전력 레벨 감도 (MIPLS: Minimum Input Power Level Sensitivity)가 -86dBm인 환경에서 SNR은 13dB, 패킷 오율 (PER: Packet Error Rate)은 1% 이하라는 높은 성능을 나타내었다. SoC 칩은 하이닉스 0.25um 상보 금속 산화 반도체 (CMOS: Complementary Metal Oxide Semiconductor) 공정을 이용하였으며 면적은 $6.52mm{\times}6.92mm$이다.