• Journal of Advanced Navigation Technology
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• v.17 no.6
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• pp.700-704
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• 2013

Quantum-dot cellular automata(QCA) is a new technology and it is an one of the alternative high performance over existing complementary metal-oxide semi-conductor(CMOS). QCA is nanoscale device and ultra-low power consumption compared with transistor-based technologies, and various circuits using QCA technology have been proposed. Binary-coded decimal(BCD), which represents decimal digits in binary, is mainly used in electronic circuits and Microprocessor, and it is comfortable in conversion operation but many data loss. In this paper, we present an BCD-EXCESS 3 Code converter which can be efficiently used for subtraction and half adjust. The proposed scheme has efficiently designed considering space and time complexities and minimization of noise, and it has been simulated and confirmed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.675-677
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• 2009

통신기기에서 중요한 기술 중 하나인 PLL(Phase Locked Loop) 회로는 주기적인 신호를 원하는 대로, 정확한 고정점으로 잡아주는데 그 목적을 둔다. 일반적인 구조로 위상주파수검출기(Phase Frequency detector), 루프필터(Loop filter), 전압제어발진기(Voltage Controlled Oscillator), 디바이더(Divider)로 구성되어진다. 그러나 일반적인 PLL 구조로는 지터(jitter)가 증가하고 트랙(tracking) 속도가 느리다는 단점이 있다. 이를 보완하기 위해 루프필터 전단에 차지펌프(Charge pump) 회로를 추가하여 사용하고 있다. 본 논문에서는 CMOS를 이용한 PLL용 차지펌프를 설계하였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 Specter로 시뮬레이션 하였으며, Virtuso2로 레이아웃 하였다.

• International journal of advanced smart convergence
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• v.12 no.4
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• pp.44-54
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• 2023

This paper provides a comprehensive analysis of the implications of the metaverse on the music industry, focusing on copyright issues and potential solutions. It delves into the concept and characteristics of metaverse platforms, describing them as environments that immerse users in a variety of virtual experiences. A significant portion of the paper is dedicated to exploring music use and copyright infringement in the metaverse. It examines how users incorporate existing music into their content, often leading to legal challenges due to copyright infringement. The paper discusses the role of online service providers (OSPs) in this context and the legal implications of their actions. The paper also addresses the 'safe harbor' provisions for OSPs and examines the balance between protecting rights holders and limiting OSP liability. It highlights the challenges and limitations of copyright enforcement in the metaverse, especially given the unique nature of content on platforms such as Roblox. Finally, the article proposes solutions to simplify music licensing in the metaverse, suggesting a shift from property rules to liability rules and the establishment of Collective Management Organizations (CMOs) to streamline the licensing process and better protect copyright holders' interests.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.2
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• pp.111-116
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• 2003

In this paper, a CMOS baseband analog receiver for wireless home network is discussed. It is composed of a Gilbert type mixer, an Elliptic 6th order 1ow pass filter, and a 6-bit A/D converter. The main role of the mixer is generating a mixed analog signal between the 200MHz output signal of CMOS RF stage and the 199MHz local oscillator. After the undesired high frequency component of the mixed signal comes out. Finally, the analog signal is converted into digital code at the 6-bit A/D converter, The proposed receiver is fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly 5-metal CMOS technology, and the chip area is 200${\mu}{\textrm}{m}$ X1400${\mu}{\textrm}{m}$. the receiver consumes 130㎽ at 2.5V power supply.

• Journal of IKEEE
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• v.13 no.2
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• pp.208-215
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• 2009

The high efficiency power management IC(PMIC) with DT-CMOS(Dynamic Threshold voltage MOSFET) switching device for portable application is proposed in this paper. Because portable applications need high output voltages and low output voltage, Boost converter and Buck converter are embedded in One-chip. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. Boost converter and Buck converter, are based on Voltage-mode PWM control circuits and low on-resistance switching device, achieved the high efficiency near 92.1% and 95%, respectively, at 100mA output current. And Step-down DC-DC converter in stand-by mode below 1mA is designed with LDO in order to achive high efficiency.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.54-62
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• 2004

In this paper, we discuss on the design of a current mode CMOS multiplier circuit over $GF(3^m)$. Using the standard basis, we show the variation of vector representation of multiplicand by multiplying primitive element α, which completes the multiplicative process. For the $GF(3^m)$ multiplicative circuit design, we design GF(3) adder and multiplier circuit using current mode CMOS technology and get the simulation results. Using the basic gates - GF(3) adder and multiplier, we build the $GF(3^m)$ multiplier circuit and show the examples for the case m=3. We also propose the assembly of the operation blocks for a complete $GF(3^m)$ multiplier. Therefore, the proposed circuit is easily extensible to other p and m values over $GF(p^m)$ and has advantages for VLSI implementation. We verify the validity of the proposed circuit by functional simulations and the results are provided.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.198-204
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• 2001

In this paper, a 3V 8-bit 200MSPS CMOS folding / interpolation A/D Converter is proposed. It employs an efficient architecture whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improved SNDR by to be low input frequency, distributed track and hold circuits are included. In order to obtain a high speed and low power operation, further, a novel dynamic latch and digital encoder based on a novel delay error correction are proposed. The chip has been fabricated with a 0.35${\mu}{\textrm}{m}$ 2-poly 3-metal n-well CMOS technology. The effective chip area is 1070${\mu}{\textrm}{m}$$\times$650${\mu}{\textrm}{m}$ and it dissipates about 230mW at 3.3V power supply. The INL is within $\pm$1LSB and DNL is within $\pm$1LSB, respectively. The SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.397-409
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• 1993

This paper proposed the design methodology of the 8 bit binary parallel adder with carry book-ahead scheme via current-mode CMOS multivalued logic and simulated the proposed adder under $5{\mu}m$ standard IC process technology. The threshold conditions of $G_K$ and $P_K$ which are needed for m-valued parallel adder with CLA are evaluated and adopted for quaternary logic. The design of quaternary CMOS logic circuits, encoder, decoder, mod-4 adder, $G_K$ and $P_K$ detecting circuit and current-voltage converter is proposed and is simulated to prove the operations. These circuits are necessary for binary arithmetic using multivalued logic. By comparing with the conventional binary adder and the CCD-MVL adder, We show that the proposed adder cab be designed one look-ahead carry generator with 1-level structure under standard CMOS technology and confirm the usefulness of the proposed adder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.57-65
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• 2002

In this paper, a 2.5V 10-bit 300MSPS CMOS D/A Converter is described. The architecture of the D/A Converter is based on a current steering 8+2 segmented type, which reduces non-linearity error and other secondary effects. In order to achieve a high performance D/A Converter, a novel current cell with a low spurious deglitchnig circuit and a novel inverse thermomeer decoder are proposed. To verify the performance, it is integrated with $0.25{\mu}m$ CMOS 1-poly 5-metal technology. The effective chip area is $1.56mm^2$ and power consumption is about 84mW at 2.5V power supply. The simulation and experimental results show that the glitch energy is 0.9pVsec at fs=100MHz, 15pVsec at fs=300MHz in worst case, respectively. Further, both of INL and DNL are within ${\pm}$1.5LSB, and the SFDR is about 45dB when sampling, frequency, is 300MHz and output frequency is 1MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.189-193
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• 2005

In this paper, we propose a direct conversion double-balanced down-converter fer MB-OFDM W system, which is implemented using $0.18\;{\mu}m$ CMOS technology and its measurement results are shown. The proposed down-converter adopts a resistive current-source instead of general transconductance stage using MOS transistor to achieve wideband characteristics over RF input frequency band $3\~5\;GHz$ with good gain flatness. The measured conversion gain is more than +3 dB, and gain flatness is less than 3 dB for three UWB channels. The dc consumption of this work is only 0.89 mA from 1.8 V power supply, leading to the low-power W application.