• 한국전자파학회논문지
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• 제13권7호
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• pp.641-648
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• 2002

The study on the chip waveform design to minimize multiple-access interference (MAI) and its performance evaluation are very important since chip waveform decides the signal quality and system capacity of the direct-sequence CDMA wireless communication system. This paper suggests the analytical chip waveform to minimize the MAI. The BER and throughput performances achieved by the proposed analytical optimum chip waveform are compared with those of the conventional chip waveforms in the Nakagami-m distribution frequency selective channel when the differential phase shift keying (DPSK) is employed in DS-CDMA system. From the numerical results, capacity and throughput are improved about 2 times and 1.4 times respectively when it is compared with the Kaiser chip waveform that is considered as one of the best in the conventional ones.

• 반도체디스플레이기술학회지
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• 제4권2호
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• pp.33-37
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• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified fer other bonding methods such as ACF.

• 한국전기전자재료학회논문지
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• 제13권7호
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• pp.583-591
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• 2000

It this paper the multilayer chip band pass filter for next generation mobile communication phone is fabricated and designed. For the design the multilayer chip filter of non-contented equivalent circuit and contented equivalent circuit with attenuation pole is presented. Finally it is fabricated and designed using the multilayer chip filter of contented equivalent circuit with attenuation pole. The size insertion loss center frequency and band width of multilayer chip filter are 4.5$\times$3.2$\times$2.0[mm], 3.0[d.B] and 1945$\pm$25 MHz respectively. The multilayer chip filter was fabricated by screen printing with Ag electrode after tape casting. Simulation results of multilayer chip filter are compared with experimental results and found to be in excellent agreements.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.924-927
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• 2003

In this paper, we design the memory tester chip set playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each chip such as sequence chip and address/data generator chip. Sequence chip controls the test sequence according to instructions saved in the memory. And Generator chip generates the address and data signals according to instructions saved in the memory, too.

• 반도체디스플레이기술학회지
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• 제8권2호
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• pp.15-21
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• 2009

Atmospheric pressure plasma equipment was successfully applied to the flip chip BGA manufacturing process to improve the uniformity of flux printing process. The problem was characterized as shrinkage of the printed flux layer due to insufficient surface energy of the flip chip BGA substrate. To improve the hydrophilic characteristics of the flip chip BGA substrate, remote DBD type atmospheric pressure plasma equipment was developed and adapted to the flux print process. The equipment enhanced the surface energy of the substrate to reasonable level and made the flux be distributed over the entire flip chip BGA substrate uniformly. This research was the first adaptation of the atmospheric pressure plasma equipment to the flip chip BGA manufacturing process and a lot of possible applications are supposed to be extended to other PCB manufacturing processes such as organic cleaning, etc.

• 한국정밀공학회지
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• 제10권4호
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• pp.206-215
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• 1993

The finite element method is applied to analyze the mechanism of metal cutting, especially micro metal cutting. This paper introduces some effects, such as constitutive deformation laws of workpiece material, friction of tool-chip contact interfaces, tool rake angle and also simulate the cutting process, chip formation and geometry, tool-chip contact, reaction force of tool. Under the usual plane strain assumption, quasi-static analysis were performed with variation of tool-chip interface friction coefficients and tool rake angles. In this analysis, cutting speed, cutting depth set to 8m/sec, 0.02mm, respectively. Some cutting parameters are affected to cutting force, plastic deformation of chip, shear plane angle, chip thickness and tool-chip contact length and reaction forces on tool. Several aspects of the metal cutting process predicted by the finite element analysis provide information about tool shape design and optimal cutting conditions.

• 전자공학회논문지
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• 제49권9호
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• pp.259-269
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• 2012

전원 전압이 낮아지고, 칩의 동작 속도가 빨라짐에 따라 온-칩 인덕턴스를 포함한 power distribution network (PDN) 분석이 중요해 질 것으로 예측된다. 본 논문에서는 일반적인 온-칩 전력 격자 구조에 적용시킬 수 있는 효과적인 인덕턴스 추출방법에 대해 제안한다. Chip layout에 적용할 수 있는 loop 인덕턴스 모델을 제시하고, 그 모델을 사용하여 post layout RC extraction netlist로 부터 인덕턴스를 포함한 netlist를 추출할 수 있는 tool을 개발하였다. 제안된 loop 인덕턴스 모델과 개발된 tool의 정확성은 회로 simulation을 통해 PEEC 모델과 비교하여 검증하였다. 인덕턴스 추출 방법을 실제 chip layout에 적용시켜 on-chip inductance를 포함한 PDN의 voltage fluctuation을 예측하였다. 패키지와 PCB 모델을 포함한 co-simulation 모델을 구성하여 on-chip inductance의 영향을 분석하였다.

• Journal of Chest Surgery
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• 제50권3호
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• pp.153-162
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• 2017

Background: The mesenchymal-epithelial transition factor (MET) receptor can be overexpressed in solid tumors, including small cell lung cancer (SCLC). However, the molecular mechanism regulating MET stability and turnover in SCLC remains undefined. One potential mechanism of MET regulation involves the C-terminus of Hsp70-interacting protein (CHIP), which targets heat shock protein 90-interacting proteins for ubiquitination and proteasomal degradation. In the present study, we investigated the functional effects of CHIP expression on MET regulation and the control of SCLC cell apoptosis and invasion. Methods: To evaluate the expression of CHIP and c-Met, which is a protein that in humans is encoded by the MET gene (the MET proto-oncogene), we examined the expression pattern of c-Met and CHIP in SCLC cell lines by western blotting. To investigate whether CHIP overexpression reduced cell proliferation and invasive activity in SCLC cell lines, we transfected cells with CHIP and performed a cell viability assay and cellular apoptosis assays. Results: We found an inverse relationship between the expression of CHIP and MET in SCLC cell lines (n=5). CHIP destabilized the endogenous MET receptor in SCLC cell lines, indicating an essential role for CHIP in the regulation of MET degradation. In addition, CHIP inhibited MET-dependent pathways, and invasion, cell growth, and apoptosis were reduced by CHIP overexpression in SCLC cell lines. Conclusion: C HIP is capable of regulating SCLC cell apoptosis and invasion by inhibiting MET-mediated cytoskeletal and cell survival pathways in NCI-H69 cells. CHIP suppresses MET-dependent signaling, and regulates MET-mediated SCLC motility.

• Journal of electromagnetic engineering and science
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• 제11권4호
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• pp.282-289
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• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• 마이크로전자및패키징학회지
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• 제25권1호
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• pp.1-10
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• 2018

최근 플렉서블 OLED, 플렉서블 반도체, 플렉서블 태양전지와 같은 유연전자소자의 개발이 각광을 받고 있다. 유연소자에 밀봉 혹은 봉지(encapsulation) 기술이 매우 필요하며, 봉지 기술은 유연소자의 응력을 완화시키거나, 산소나 습기에 노출되는 것을 방지하기 위해 적용된다. 본 연구는 봉지막(encapsulation layer)이 반도체 칩의 내구성에 미치는 영향을 고찰하였다. 특히 다층 구조 패키지의 칩의 파괴성능에 미치는 영향을 칩의 center crack에 대한 파괴해석을 통하여 살펴보았다. 다층구조 패키지는 폭이 넓어 칩 위로만 봉지막이 덮고있는 "wide chip"과 칩의 폭이 좁아 봉지막이 칩과 기판을 모두 감싸고 있는 "narrow chip"의 모델로 구분하였다. Wide chip모델의 경우 작용하는 하중조건에 상관없이 봉지막의 두께가 두꺼울수록, 강성이 커질수록 칩의 파괴성능은 향상된다. 그러나 narrow chip모델에 인장이 작용할 때 봉지막의 두께가 두껍고 강성이 커질수록 파괴성능은 악화되는데 이는 외부하중이 바로 칩에 작용하지 않고 봉지막을 통하여 전달되기에 봉지막이 강하면 강한 외력이 칩내의 균열에 작용하기 때문이다. Narrow chip모델에 굽힘이 작용할 경우는 봉지막의 강성과 두께에 따라 균열에 미치는 영향이 달라지는데 봉지막의 두께가 작을 때는 봉지막이 없을 때보다 파괴성능이 나쁘지만 강성과 두께의 증가하면neutral axis가 점점 상승하여 균열이 있는 칩이 neutral axis에 가까워지게 되므로 균열에 작용하는 하중의 크기가 급격히 줄어들게 되어 파괴성능은 향상된다. 본 연구는 봉지막이 있는 다층 패키지 구조에 다양한 형태의 하중이 작용할 때 패키지의 파괴성능을 향상시키기 위한 봉지막의 설계가이드로 활용될 수 있다.