• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.68-73
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• 2013

In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.

• Journal of IKEEE
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• v.14 no.1
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• pp.65-74
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• 2010

The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.2
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• pp.151-160
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• 1997

In this paper, we have carried out the DS/CDMA with a suppressed pilot channel, which is used in receiving coherently with Rake diversity and in synchronizing the chip timing, in the mobile satellite communication. Also, we have investigated the envelope variation of a shadowed Rician fading simulator, and analyzed the error performences of DS/CDMA in the mobile satellite communication. The results showed that the error performance in the Heavy shadowing environment might be degraded more than in the Rayleigh fading environment since the fading envelopes in the former environment are varied randomly compared with those in the latter environment. And the performence of DS/CDMA system could be improved about 10 dB compared with that of narrowband QPSK system. In conclusion, DS/CDMA with a suppressed pilot channel had the best performance in the case of the suppressed pilot channel to transmission power ratio $\beta$=-8 dB, the number of complex delay profiles $N_{profile}$=32, and using these values, the error performance of DS/CDMA in Light shadowing environment was identical to the ideal QPSK error performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1350-1359
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• 2008

This paper presents a wideband doubly balanced resistive mixer fabricated using $0.5{\mu}m$ GaAs p-HEMT process. Three baluns are employed in the mixer. LO and RF baluns operating over an 8 to 20 GHz range were implemented with Marchand baluns. In order to reduce chip size, the Marchand baluns were realized by the meandering multicoupled line and inductor lines were inserted to compensate for the meandering effect. IF balun was implemented through a DC-coupled differential amplifier. The size of IF balun is $0.3{\times}0.5\;mm^2$ and the measured amplitude and phase unbalances were less than 1 dB and $5^{\circ}$, respectively from DC to 7 GHz. The mixer is $1.7{\times}1.8\;mm^2$ in size, has a conversion loss of 5 to 11 dB, and an output third order intercept(OIP3) of +10 to +15 dBm at 16 dBm LO power for the operating bandwidth.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.844-853
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• 2008

This paper describes the design of a FEM(Front End Module) having power detection function for mobile handset application. The designed FEM consists of a MMIC(Monolithic Microwave Integrated Circuits) power amplifier chip, SAW Tx filter and duplexer, diode power detector and stripline matching circuit. An LTCC(Low Temperature Co-fired Ceramics) technology is adopted for miniaturized FEM. The frequency band is $824{\sim}869$ MHz which is the uplink Tx band of the CDMA mobile system. The size of designed FEM is $7.0{\times}5.5{\times}1.5\;mm^3$, which is an ultra-small size even though the power detector circuit is included. All sub-components of FEM have been developed and measured in advance before being integrated into FEM. The measured output power and gain are 27 dBm and 27 dB, respectively. In addition, the measured ACPR characteristics are 46.59 dBc and 55.5 dBc at 885 kHz and 1.98 MHz offset, respectively.

• Journal of Gastric Cancer
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• v.16 no.4
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• pp.221-229
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• 2016

Purpose: Dysregulated microRNAs (miRNAs) can contribute to cancer development by leading to abnormal proliferation of cells, apoptosis, and differentiation. Although several miRNAs that are related to gastric cancer have been identified, the reported results have been inconsistent. The aim of this study was to determine miRNA expression profiles and validate miRNAs up- and down-regulated in gastric cancer. Materials and Methods: We evaluated 34 primary gastric cancer tissues and paired adjacent nontumorous gastric tissues. Total RNA was extracted, and low-molecular-weight RNAs (<200 nucleotides) were isolated for further analysis. Two pairs of tissues were processed for GeneChip microarray analysis, and the identified up- and down-regulated miRNAs were validated by real-time quantitative polymerase chain reaction (qPCR). Results: In the set of differentially expressed miRNAs, 5 were overexpressed by more than 2 fold, and 5 were reduced by 2 fold or less in gastric cancer tissues compared with normal gastric tissues. Four of these miRNAs (miR-196b-5p, miR-375, miR-483-5p, and miR-486-5p) were then validated by qPCR, and the relative expression levels of 2 miRNAs (miR-196b-5p and miR-375) were significantly different between cancer and normal tissues. Conclusions: Our results revealed that the expression of miR-196b-5p and miR-375 significantly correlates with gastric cancer. These miRNAs could therefore serve as diagnostic biomarkers of gastric cancer.

• Journal of Mechanical Science and Technology
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• v.18 no.5
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• pp.770-779
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• 2004

This paper describes the micro cutting of wear resistant tungsten carbides using PCD (Poly-Crystalline Diamond) cutting tools in performance with SEM (Scanning Electron Microscope) direct observation method. Turning experiments were also carried out on this alloy (V50) using a PCD cutting tool. One of the purposes of this study is to describe clearly the cutting mechanism of tungsten carbides and the behavior of WC particles in the deformation zone in orthogonal micro cutting. Other purposes are to achieve a systematic understanding of machining characteristics and the effects of machining parameters on cutting force, machined surface and tool wear rates by the outer turning of this alloy carried out using the PCD cutting tool during these various cutting conditions. A summary of the results are as follows: (1) From the SEM direct observation in cutting the tungsten carbide, WC particles are broken and come into contact with the tool edge directly. This causes tool wear in which portions scrape the tool in a strong manner. (2) There are two chip formation types. One is where the shear angle is comparatively small and the crack of the shear plane becomes wide. The other is a type where the shear angle is above 45 degrees and the crack of the shear plane does not widen. These differences are caused by the stress condition which gives rise to the friction at the shear plane. (3) The thrust cutting forces tend to increase more rapidly than the principal forces, as the depth of cut and the cutting speed are increased preferably in the orthogonal micro cutting. (4) The tool wear on the flank face was larger than that on the rake face in the orthogonal micro cutting. (5) Three components of cutting force in the conventional turning experiments were different in balance from ordinary cutting such as the cutting of steel or cast iron. Those expressed a large value of thrust force, principal force, and feed force. (6) From the viewpoint of high efficient cutting found within this research, a proper cutting speed was 15 m/min and a proper feed rate was 0.1 mm/rev. In this case, it was found that the tool life of a PCD tool was limited to a distance of approximately 230 m. (7) When the depth of cut was 0.1 mm, there was no influence of the feed rate on the feed force. The feed force tended to decrease, as the cutting distance was long, because the tool was worn and the tool edge retreated. (8) The main tool wear of a PCD tool in this research was due to the flank wear within the maximum value of $V_{max}$ being about 260 $\mu\textrm{m}$.