• 센서학회지
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• 제25권2호
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• pp.143-147
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• 2016

Characteristics of the conventional gold (Au) surface plasmon resonance (SPR) chip, bi-metallic(Au/silver (Ag)) SPR chip, and tri-metallic(Au/Ag/Au) SPR chip were investigated and compared in the intensity measurement mode for the enhancement of SPR image sensor reactivity. Reflectance curves of the Au, bi- and tri-metallic SPR chips were acquired in phosphate-buffered saline (PBS) solution and were compared. The line width of the reflectance curve of the bi-metallic chip was the narrowest among the three different types of the chips. Also, the tangential slope of the bi-metallic chip was steeper than those of the other chips. Various concentrations of bovine serum albumin (BSA) were utilized in the SPR experiment. As a result, among the above three chips reflectance variation value of the bi-metallic chip was the largest.

• 마이크로전자및패키징학회지
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• 제18권1호
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• pp.41-47
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• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권7호
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• pp.328-334
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• 2002

The DNA chips are devices associating the specific recognition properties of two DNA single strands through hybridization process with the performances of the microtechnology. In the literature, the "Gene chip" or "DNA chip" terminology is employed in a wide way and includes macroarrays and microarrays. Standard definitions are not yet clearly exposed. Generally, the difference between macro and microarray concerns the number of active areas and their size, Macroarrays correspond to devices containing some tens spots of 500$\mu$m or larger in diameter. microarrays concern devices containing thousnads spots of size less than 500$\mu$m. The key technical parameters for evaluating microarray-manufacturing technologies include microarray density and design, biochemical composition and versatility, repreducibility, throughput, quality, cost and ease of prototyping. Here we report, a new method in which minute particles are arranged in a random fashion on a chip pattern using random fluidic self-assembly (RFSA) method by hydrophobic interaction. We intend to improve the stability of the particles at the time of arrangement by establishing a wall on the chip pattern, besides distinction of an individual particle is enabled by giving a tag structure. This study demonstrates the fabrication of a chip pattern, immobilization of DNA to the particles and arrangement of the minute particle groups on the chip pattern by hydrophobic interaction.ophobic interaction.

• ETRI Journal
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• 제19권3호
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• 자원리싸이클링
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• 제6권4호
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• pp.24-30
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• 1997

최근 금속 스크랩의 재활용에 있어서 고품질의 2차지금을 제조하고자 하는 연구가 진행되고 있다. 본 연구에서는 알루미늄 주조품의 기계가공 후 발생하는 알루미늄 Chip을 보다 효율적이고 신속하게 재활용하기 위하여 vortex melting법을 수행하였다. Vortex melting 기술을 chip의 용해공정에 도입하였다. 최적의 vortex 깊이는 수모델 실험을 통하여 결정되었는데, 교반자의 형상, 위치, 회전속도 및 수위 등에 의해 결정된다. Chip의 용해전 상온, 200, 300, $400^{\circ}C$에서 예열하여 vortex의 중앙에 투입하엿다. 따라서, 온도에 따른 회수율을 결정할 수 있었다. 본 실험의 결과로서, 최적의 vortex 깊이는 교반자의 형상, 회전속도에 의해서만 영향을 받으며, 최고의 회수율, 97%는 chip의 예열온도가 $300^{\circ}C$일 경우 얻어졌다.

• 한국기계가공학회지
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• 제12권6호
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• pp.175-181
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• 2013

The primary element of machining automation is to maximize the utilization of machine tools, which determines the output and lead-time. In particular, 95% of raw materials for wing ribs are cut into chips and 0.6 ton of chips are generated every hour from each machine tool. In order to verify the chip recycling system that controls the chips from the machines in five-axis FMS line, a simulation of the virtual model is constructed using the QUEST simulation program. The optimum speed of the chip conveyor and its operating conditions that directly affect the efficiency of the FMS line are presented including the chip conveyor speed, the maximum capacity of the hopper, and the number of chip compressors.

• 한국정보통신학회논문지
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• 제11권8호
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• pp.1564-1573
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• 2007

현재 사용 중인 프린터의 토너에 부착된 토너 잔량 검출 회로는 PCB 회로기판을 사용함으로써 부피가 비교적 큰 상태이므로 보다 경량 소형화된 프린트에 사용하기에는 부적합하다. 본 연구에서는 이와같은 소형화된 회로를 one chip함으로써 경쟁력이 있는 제품을 개발한다. 2005년 이후 출시 된 프린터에 사용되는 토너에는 칩이 필수적으로 부착되어야 한다. 따라서 앞으로의 재생시장에서 사용될 칩의 수요는 점점 커질 것이다. 세계적인 레이저 프린터 메이커들이 프린터에서 사용되는 토너카트리지의 정보를 관리하여 고객 서비스를 한다는 취지로 프린터에 부착되는 칩으로 인해 재생토너의 생산이 불가능하다. 본 연구에서는 재생토너를 생산하기 위해 필수적으로 부착되는 칩을 개발한다.

• Journal of the Korean Physical Society
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• 제73권9호
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• pp.1346-1350
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• 2018

An electrode-evaporation technology on both the top and bottom sides of the bare vertical-type single chip separated from the traditional substrate by cooling, was developed for III-nitride vertical-type single chip LEDs with thick GaN epilayer. The post-process of the cooling step was followed by sorting the bare vertical-type single chip LEDs into the holes in a pocket-type shadow mask for deposition of the electrodes at the top and bottom sides of bare vertical-type single chip LEDs without the traditional substrate for electrode evaporation technology for vertical-type single chip LEDs. The variation in size of the hole between the designed shadow mask and the deposited electrodes owing to the use of the designed pocket-type shadow mask is investigated. Furthermore, the electrical and the optical properties of bare vertical-type single chip LEDs deposited with two different shapes of n-type electrodes using the pocket-type shadow mask are investigated to explore the possibility of the e-beam evaporation method.

• 대한기계학회논문집A
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• 제28권9호
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• pp.1408-1414
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• 2004

The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF (anisotropic conductive film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue lift of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear hi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2$^{nd}$ DOE was conducted to obtain RSM equation far the choose 3 design parameter. The coefficient of determination ($R^2$) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430$\mu$m, and 78$\mu$m, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter should be controlled within 3% of average value.

• 아시안잔디학회지
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• 제16권1호
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• pp.19-30
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• 2002

경직된 지반의 물리성 개선재로서 rubber chip의 토양 내 혼합 또는 배토는 잔디의 생육과 지반의 이·화학성 및 중금속 추출 실험을 통하여 다음과 같은 결론을 얻었다. Rubber chip의 토양 내 혼합은 지면의 온도 상승효과를 가져왔으며 이는 겨울철의 동해방지 및 맹아출현기를 앞당길 수 있을 것이라 추정된다. 그러나 복사열이 높은 여름에는 rubber chip에 의한 표면, 지중 온도의 상승으로 잔디의 피해가 우려된다. 또한 토양 내에 rubber chip의 혼합함량(rubber chip 20%, 40%)이 많을수록 잔디의 발아와 생육 및 피복에 부정적인 영향을 끼쳤다. Rubberchip의 토양혼합은 지반의 이·화학성 변화에 크게 작용하지 않았으며 중금속 추출실험에서도 차이를 나타내지 않아 토양환경 오염이 없을 것으로 판단된다. Rubber chip을 배토용 재료로서 사용했을 경우, 경직된 토양구조를 개선시켜 주었다. 특히 통기작업 후 rubber chip의 배토는 지반의 표면탄성을 현저히 완화시켰다. 따라서 현재 우리나라에서 보수중이 거나 건설중인 연습구장, 보조구장에 재활용이 가능한 폐타이어 rubber chip을 지반 답압 개선용, 배토용 재료로서 사용이 가능할 것으로 판단된다.