• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.5
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• pp.1-7
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• 2008

The general bus architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. Specially, as several masters do not concurrently receive the right of bus usage, the arbiter plays an important role in arbitrating between shared bus and masters. Fixed priority, round-robin, TDMA and Lottery methods are developed in general arbitration policies, which lead the efficiency of bus usage in shared bus. On the other hand, the bus architecture can be modified to maximize the system performance. In the paper, we propose the flying master bus architecture that supports the parallel bus communication and analyze its merits and demerits following various arbitration policies that are mentioned above, compared with normal shared bus. From the results of performance verification using TLM(Transaction Level Model), we find that more than 40% of the data communication performance improves, regardless of arbitration policies. As the flying master bus architecture advances its studies and applies various SoCs, it becomes the leading candidate of the high performance bus architecture.

• KIEE International Transactions on Power Engineering
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• v.5A no.2
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• pp.177-185
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• 2005

This paper proposes an expert system that can enhance the accuracy of real-time bus reconfiguration strategy by adopting the local minimum tree search method and that can minimize the spreading effect of the fault by considering the operating condition when a main transformer fault occurs in an automated substation. The local minimum tree search method is used to expand the best-first search method. This method has the advantage that it can improve the solution performance within the limits of the real-time condition. The inference strategy proposed expert system consists of two stages. The first stage determines the switching candidate set by searching possible switching candidates starting from the main transformer or busbar related to the event. The second stage determines the rational real-time bus reconfiguration strategy based on heuristic rules from the obtained switching candidate set. Also, this paper proposes generalized distribution substation modeling using graph theory, and a substation database based on the study results is designed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2433-2438
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• 2011

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, bus system performance can be changed definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this study, we proposed the score arbitration method and synthesized it using Hynix 0.18um technology, after design of RTL. Also we analyze the performance compared with general arbitration methods through simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.35-44
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• 2005

SoC(systnn-on-a-chip) requires high bandwidth system bus for performing multiple functions. Performance of the system is affected by bandwidth of the system bus. In this paper, for efficient management of the bus resource on a SoC platform, we present a latency model of the shared bus organized by multiple layers. Using the latency model, we can analyze latencies of the shared bus on a SoC. Moreover we evaluate a throughput of the bus and compare with needed throughput of the SoC platform including IPs such as MPEG or USB 2.0. And we can use the results as a criteria to find out an optimal bus architecture for the specific SoC design. For verifying accuracy of the proposed model, we compared the latencies with the simulation result from MaxSim tools. As the result of simulation, the accuracy of the IS model for a single layer and multiple layer are over $96\%\;and\;85\%$ respectively.

• Transactions of the Korean Society of Automotive Engineers
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• v.18 no.6
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• pp.138-144
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• 2010

If the vibration is occurred in a large-sized bus roof, it makes people annoying and complaining the quality of a large-sized bus. So in design stage, it must be considered. To assess vibration at the roof which is equipped with air conditioner in design stage, finite element model is constructed. Computer simulation analysis and experimental method are performed. The dynamic characteristics of the large-sized bus are found by using eigenvalue method. It is related with dynamic behavior. The running conditions of a large-sized bus are velocity and road condition which followed experimental conditions. And the frequency response of a large-sized bus is well correlated with analysis result. Modal participation method is used for finding major modes at each peak. Using this method, we found that front and rear suspension system, engine mounting system and roof structure are the major reasons of the roof vibration. To reduce vibration level of roof in a large-sized bus, spring stiffness of front and rear suspension system, spring stiffness of engine mounting system and roof structure are properly combined. From this study, the vibration characteristics of the roof structure of a large-sized bus can be to a satisfactory level.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.518-521
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• 2018

As public transportation use increases, studies are being conducted to consider user convenience using IoT data collected via the bus information system. A low-floor bus means a bus that is designed to be 20 cm lower than a normal bus and can be wheelchair-accessible. However, the system in which the transportation weak is provided to use the low-floor bus is less than the system provided to the general user. In order to use the low-floor bus smoothly, as in the case of the general user, the service system for the weak driver is needed. In this paper, a low - floor bus reservation system is designed to provide a service for low - rise bus users to conveniently use low - floor buses.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.288-299
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• 1993

This paper proposes the new bus protocol in the tightly coupled multiprocessor system. The bus protocol uses the pipelined data transfer and block transfer scheme to increase the bus bandwidth, The bus also has the independent transfer lines for the address and data respectively, and it can transfer the data up to maximum 264 Mbytes /sec. This paper also models the multiprocessor system where each processor boards have the private cache. Simulation evaluates the bus and system performance according to hit ratio of the reference data in cache memory, In the case of using this bus, the bus is evaluated not to be saturated when up to 10 processor boards are connected to the bus. As for up to 4 memory interleavng, the performance increases linearly.

• International Journal of Highway Engineering
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• v.15 no.2
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• pp.159-167
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• 2013

PURPOSES : In this study, the effects of when median exclusive bus lanes were applied to Daejeon trunk road (Wolpyeng crossway~Seodaejeon crossway, 6.3km) and (Daeduck Bridge 4~Kyeryong 4, 2.6km) by Microscopic Simulation VISSIM (5.0) was studied. The median exclusive bus lanes are one of the measures of transportation system manage techniques that can especially improve the efficiency of public transportation facilities. METHODS : According to the analysis of VISSIM on the Gyerong mainroad and Daedeok mainroad, when the median exclusive bus lanes were applied unlike when the roadside bus-only lanes were applied, the average travel speed of vehicles decreased but the average delay time and travel time increased. This arised from the changes in the geometric structure of the road which occurred the reduction of vehicle lane in the center of the road. RESULTS : In the case of bus, on the other hand, the average travel speed increased but the average delay time and travel time decreased. This is because the problems such as illegal parking and stopping, secondary road in out vehicle, and conflict of intersection right turn that roadside bus-only lanes occurred was solved. CONCLUSIONS : Although the introduction of median exclusive bus lanes will have a negative effect on general traffic flow due to the aggravation of travel, decrease of passenger car usage will lead to decrease of traffic volume. Therefore, smooth vehicle travel is expected.

• Journal of electromagnetic engineering and science
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• v.6 no.4
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• pp.197-202
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• 2006

This paper presents a study on the differential signaling for the rectangular power-bus structure. The full-wave modal analysis method analyzes how the differential-signaling can lower the power-bus resonance noise levels. The methodology is validated by the use of the FDTD method and reference measurements.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1653-1658
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• 2009

SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. In this study, we compare the characteristics of various arbitration policies using TLM(Transaction Level Model) method. Fixed priority, round-robin, TDMA and Lottery bus policies are used in general arbitration method. We analyze the merit and demerit of these arbitration policies.