• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.05a
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• pp.227-229
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• 1995

Using thermal oxide SiO$_2$ as a dielectrical isolation layer, SOI Hall sensors without pn junction isolation have been fabricated on Si/SiO$_2$/Si structures. The SOI structure was formed by SDB (Si- wafer direct bonding) technology. The Hall voltage and the sensitivity of Si Hall devices implemented on the SDB SOI structure show good linearity with respect to the appled magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall device is average 600V/V.T. In the trmperature range of 25 to 300$^{\circ}C$, the shifts of TCO(Temperature Coefficient of the Offset Voltage) and TCS(Temperature Coefficient of the Product Sensitivity) are less than ${\pm}$ 6.7x10$\^$-3/ C and ${\pm}$8.2x10$\^$04/$^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of Hall sensors with a high-sensitivity and high-temperature operation.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.2
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• pp.216-223
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• 1997

By using aluminum iso - propoxide($Al(OC_3H_7)_3$, AIP), $Al_2O_3$thin films were deposited on (100) single crystal silicon wafer by MOCVD method. The compositions of deposited films were analysed by electron spectroscopy for chemical analyse(ESCA). The morphology and thickness of the deposited films were characterized by scanning electron microscopy. The refractive index and C-V propertied were studied by using ellipsometery and HP4192A, respectively. From the results of ESCA and SEM analysis at low pressure, more uniform and stable stoichiometric film can be obtained compared with that of atmospheric pressure. For optical film usage, required refractive index can be obtained by heat treatment of deposited film. To improve C -V characteristics in NMOS device, it is requred to control OH-which is mobile charge in oxide, to form $SiO_2$ layer between $Al_2O_3$ and Si by heat treatment.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• 한국신재생에너지학회:학술대회논문집
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• 2009.06a
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• pp.172-175
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• 2009

n-type crystalline silicon wafers were passivated with intrinsic a-Si:H thin films on both sides using HWCVD. Minority carrier lifetime measurement was used to verify interface passivation properties between a-Si:H thin film and crystalline Si wafer. Thin film interface characteristics were investigated depending on $H_2/SiH_4$ ratio and hot wire deposition temperature. Vacuum annealing were processed after deposition a-Si:H thin films on both sides to investigate thermal effects from post process steps. We noticed the effect of interface passivation properties according to $H_2/SiH_4$ ratio and hot wire deposition temperature, and we had maximum point of minority carrier lifetime at H2/SiH4 10 ratio and $1600^{\circ}C$ wire temperature.

• Journal of the Korean Vacuum Society
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• v.11 no.1
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• pp.16-21
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• 2002

Selective epitaxial growth(SEG) of silicon were performed at low temperature under an ultraclean environment below $1000^{\circ}C$ using ultraclean $Si_2H_6$ and $H_2$ gases ambient in low pressure chemical vapor deposition(LPCVD). As a result of ultraclean processing, epitaxial Si layers with good quality were obtained for uniform and SEG wafer at temperatures range 600~$710^{\circ}C$ and an incubation period of Si deposition only on $SiO_2$ was found. Low-temperature Si selectivity deposition condition and epitaxy on Si were achieved without addition of HCl. The epitaxial layer was found to be thicker than the poly layer deposited over the oxide. Incubation period prolonged for 20~30 sec can be obtained by $O_2$addition. The surface morphologies & cross sections of the deposited films were observed with SEM, The structure of the Si films was evaluated XRD.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.539-542
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• 2001

In SiC semiconductor device processing, it needs high temperature anneal for activation of ion implanted dopants. The macrosteps, 7~8nm in height, are formed on the surface of SiC substrates during activation anneal. We have investigated the effect of thermally-grown SiO$_2$layer on the suppression of macrostep formation during high temperature anneal. The cap oxide layer was found to be efficient for suppression of macrostep formation even though the annealing temperature is as high as the melting point of SiO$_2$. The thin cap oxide layer (10nm) was evaporated during anneal then the macrosteps were formed on SiC substrate. On the other hand the thicker cap oxide layer (50nm) remains until the anneal process ends. In that case, the surface was smoother and the macrosteps were rarely formed. The thermally-grown oxide layer is found to be a good material for the suppression of macrostep formation because of its feasibility of growing and processing. Moreover, we can choose a proper oxide thickness considering the evaporate rate of SiO$_2$at the given temperature.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.883-888
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS(micro electro mechanical system) fields because of its application possibility in harsh environments. This paper presents pre-bonding techniques with variation of HF pre-treatment conditions for SiC wafer direct bonding using PECVD(plasma enhanced chemical vapor deposition) oxide. The PECYD oxide was characterized by XPS(X-ray photoelectron spectrometer) and AFM(atomic force microscopy). The characteristics of the bonded sample were measured under different bonding conditions of HF concentration and an applied pressure. The bonding strength was evaluated by the tensile strength method. The bonded interface was analyzed by using SEM(scanning electron microscope). Components existed in the interlayer were analyzed by using FT-IR(fourier transform infrared spectroscopy). The bonding strength was varied with HF pre-treatment conditions before the pre-bonding in the range of 5.3 kgf/cm$^2$to 15.5 kgf/cm$^2$.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.1
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• pp.5-12
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• 2000

As a semiconductor material for electronic devices operated under extreme environmental conditions, silicon carbides (SiCs) have been intensively studied because of their excellent electrical, thermal and other physical properties. The growth characteristics of single- crystalline 6H-SiC homoepitaxial layers grown by a thermal chemical vapor deposition (CVD) were investigated. Especially, the successful growth condition of 6H-SiC homoepitaxial layers using a SiC-uncoated graphite susceptor that utilized Mo-plates was obtained. The CVD growth was performed in an RF-induction heated atmospheric pressure chamber and carried out using off-oriented ($3.5^{\circ}$tilt) substrates from the (0001) basal plane in the <110> direction with the Si-face side of the wafer. In order to investigate the crystallinity of grown epilayers, Nomarski optical microscopy, transmittance spectra, Raman spectroscopy, XRD, Photoluninescence (PL) and transmission electron microscopy (TEM) were utilized. The best quality of 6H-SiC homoepitaxial layers was observed in conditions of growth temperature $1500^{\circ}C$ and C/Si flow ratio 2.0 of $C_3H_8$ 0.2 sccm & $SiH_4$ 0.3 sccm.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.214-217
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• 2006

p-type 비정질 실리콘 에미터와 n-type 실리콘 기판의 계면에 intrinsic 비정질 실리콘을 증착함으로써 계면의 재결합을 억제하여 20%가 넘는 효율을 보이는 이종접합 태양전지가 Sanyo에 의해 처음 제시된 후 intrinsic layer에 대한 연구가 많이 진행되어 왔다. 하지만 p-type wafer의 경우는 n-type에 비해 intrinsic buffer의 효과가 미미하거나 오히려 특성을 저하시킨다는 보고가 있으며 그 이유로는 minority carrier에 대한 barrier가 상대적으로 낮다는 것과 partial epitaxy가 발생하기 때문으로 알려져 있다. 본 연구에서는 partial epitaxy를 억제하기 위한 방법으로 증착 온도를 낮추고 QSSPC를 사용하여 minority carrier lifetime을 측정함으로써 각 온도에 따른 passivation 특성을 평가하였다. 또한 SiH4에 H2를 섞어서 증착하였을 경우 각 dilution ratio(H2 flow/SiH4 flow)에서의 passivation 특성 또한 평가하였다. 기판 온도 $100^{\circ}C$에서 증착된 샘플의 lifetime이 가장 길었으며 그 이하와 이상에서는 lifetime이 감소하는 경향을 보였다 낮은 온도에서는 박막 자체의 결함이 증가하였기 때문이며 높은 온도에서는 partial epitaxy의 영향으로 추정된다. H2 dilution을 하여 증착한 샘플의 경우 SiH4만 가지고 증착한 샘플보다 훨씬 높은 lifetime을 가졌다 이 또한 박막 FT-IR결과로부터 H2 dilution을 한 경우 compact한 박막이 형성되는 것을 확인할 수 있었는데 radical mobility 증가에 의한 박막 특성 향상이 원인으로 생각된다.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1431-1433
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• 1995

This paper describes the characteristics of Si Hall sensors fabricated on a SOI(Si-on-insulator} structure, in which the SOI structure was forrmed by SDB(Si-wafer direct bonding) technology. The Hall voltage and the sensitivity of implemented Si Hall devices show good linearity with respect to the applied magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall device is average $600V/A{\cdot}T$. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(Temperature Coefficient of the Offset Voltage) and TCS(Temperature Coefficient of the product Sensitivity) are less than ${\pm}6.7{\times}10^{-3}/^{\circ}C$ and ${\pm}8.2{\times}10^{-4}/^{\circ}C$, respectively. From these results, Si Hall sensors using the SOI structure presented here are very suitable for high-temperature operation.