• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2002년도 춘계학술대회 논문집
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• pp.660-665
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• 2002

Mirror surface finish of Si-wafers has been achieved by rotary in-feed machining with cup-type wheels in ELID grinding. But the diameter of the workpiece is limited with the diameter of grinding wheel in the in-feed machining method. In this study, grinding experiments by the rotary surface grinding machine with straight type wheels ware conducted, by which the possible grinding area of the workpiece is independent of the diameter of the wheels. For the purpose of investigating the grinding characteristics of large scale diametrical silicon wafer, grinding conditions such as rotation speed of grinding wheels and revolution of workpieces are varied, and grinding machine used in this experiment is rotary type surface grinding n/c equipment with an ELID wit. The surface ground using the SD8000 wheels showed that mirror like surface roughness can be attained near 2 - 6 nm in Ra.

• Journal of Welding and Joining
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• 제24권2호
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 추계학술발표대회
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• pp.36.2-36.2
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• 2009

Low dielectric materials have been great attention in the semiconductor industry to develop high performance interlayer dielectrics with low k for Cu interconnect technology. In our study, the dielectric properties of SiOC /SiO2 thin film derived from polyphenylcarbosilane were investigated as a potential interlayer dielectrics for Cu interconnect technology. Polyphenylcarbosilane was synthesized from thermal rearrangement of polymethylphenylsilane around $350^{\circ}C{\sim}430^{\circ}C$. Characterization of synthesized polyphenylcarbosilane was performed with 29Si, 13C, 1H NMR, FT-IR, TG, XRD, GPC and GC analysis. From FT-IR data, the band at 1035 cm-1 is very strong and assigned to CH2 bending vibration in Si-CH2-Si group, indicating the formation of the polyphenylcarbosilane. Number average of molecular weight (Mn) of the polyphenylcarbosilane synthesized at $400^{\circ}C$ for 6hwas 2, 500 and is easily soluble in organic solvent. SiOC/SiO2 thin film was fabricated on ton-type silicon wafer by spin coating using 30wt % polyphenylcarbosilane incyclohexane. Curing of the film was performed in the air up to $400^{\circ}C$ for 2h. The thickness of the film is ranged from $1{\mu}m$ to $1.7{\mu}m$. The dielectric constant was determined from the capacitance data obtained from metal/polyphenylcarbosilane/conductive Si MIM capacitors and show a dielectric constant as low as 2.5 without added porosity. The SiOC /SiO2 thin film derived from polyphenylcarbosilane shows promising application as an interlayer dielectrics for Cu interconnect technology.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.196-197
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• 2010

NAND형 charge trap flash (CTF) non-volatile memory (NVM) 소자가 30nm node 이하로 고집적화 되면서, 기존의 SONOS형 CTF NVM의 tunnel barrier로 쓰이는 SiO2는 direct tunneling과 stress induced leakage current (SILC)등의 효과로 인해 data retention의 감소 등 물리적인 한계에 이르렀다. 이에 따라 개선된 retention과 빠른 쓰기/지우기 속도를 만족시키기 위해서 tunnel barrier engineering (TBE)가 제안되었다. TBE NVM은 tunnel layer의 전위장벽을 엔지니어드함으로써 낮은 전압에서 전계의 민감도를 향상 시켜 동일한 두께의 단일 SiO2 터널베리어 보다 빠른 쓰기/지우기 속도를 확보할 수 있다. 또한 최근에 각광받는 high-k 물질을 TBE NVM에 적용시키는 연구가 활발히 진행 중이다. 본 연구에서는 Si3N4와 HfAlO (HfO2 : Al2O3 = 1:3)을 적층시켜 staggered의 새로운 구조의 tunnel barrier Capacitor를 제작하여 전기적 특성을 후속 열처리 온도와 방법에 따라 평가하였다. 실험은 n-type Si (100) wafer를 RCA 클리닝 실시한 후 Low pressure chemical vapor deposition (LPCVD)를 이용하여 Si3N4 3 nm 증착 후, Atomic layer deposition (ALD)를 이용하여 HfAlO를 3 nm 증착하였다. 게이트 전극은 e-beam evaporation을 이용하여 Al를 150 nm 증착하였다. 후속 열처리는 수소가 2% 함유된 질소 분위기에서 $300^{\circ}C$와 $450^{\circ}C$에서 Forming gas annealing (FGA) 실시하였고 질소 분위기에서 $600^{\circ}C{\sim}1000^{\circ}C$까지 Rapid thermal annealing (RTA)을 각각 실시하였다. 전기적 특성 분석은 후속 열처리 공정의 온도와 열처리 방법에 따라 Current-voltage와 Capacitance-voltage 특성을 조사하였다.

• 한국표면공학회지
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• 제24권4호
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• pp.206-214
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• 1991

In the basic study of selective electroless Ni plating of Si wafers, plating rate and physical properties are investigated to obtain optimum conditions of contact hole filling. Si wafers are excellently activated in the concentration of 0.5M IF, 1mM PdCl2, 2mM EDTA at $70^{\circ}C$, 90sec. The optimum condition of Ni-B deposition on p-type Si wafers is 0.1M NiSO4, 0.11M Citrate, $70^{\circ}C$, pH6.8, 8mM DMAB. The main factor in the sheet resistences variation of films is amorphous and on heat treating matrix was transformed into a stable phase (Ni+Ni3B) at $300-400^{\circ}C$. But pH or DMAB concentration in the plating solution doesn't play role of heat-affected phase change.

• 한국재료학회지
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• 제26권8호
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• pp.401-405
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• 2016

The cobalt silicides were investigated for employment as a catalytic layer for a DSSC. Using an E-gun evaporation process, we prepared a sample of 100 nm-thick cobalt on a p-type Si (100) wafer. To form cobalt silicides, the samples were annealed at temperatures of $300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$ for 30 minutes in a vacuum. Four-point probe, XRD, FE-SEM, and CV analyses were used to determine the sheet resistance, phase, microstructure, and catalytic activity of the cobalt silicides. To confirm the corrosion stability, we also checked the microstructure change of the cobalt silicides after dipping into iodide electrolyte. Through the sheet resistance and XRD results, we determined that $Co_2Si$, CoSi, and $CoSi_2$ were formed successfully by annealing at $300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$, respectively. The microstructure analysis results showed that all the cobalt silicides were formed uniformly, and CoSi and $CoSi_2$ layers were very stable even after dipping in the iodide electrolyte. The CV result showed that CoSi and $CoSi_2$ exhibit catalytic activities 67 % and 54 % that of Pt. Our results for $Co_2Si$, CoSi, and $CoSi_2$ revealed that CoSi and $CoSi_2$ could be employed as catalyst for a DSSC.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.42-45
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• 1992

The poly silicon thin films were prepared by solid phase crystallization at 600$^{\circ}C$ of amorphous silicon films deposited on Corning 7059 glass and (100) silicon wafer with thermally grown SiO$_2$substrate by plasma enhanced chemical vapor deposition with varying rf power, deposition temperature, total flow rate. Crystallization time, microstructure, absorption coefficients were investigated by RAMAN, XRD analysis and UV transmittance measurement. Crystallization time of amorphous silicon films was increased with increasing rf power, decreasing deposition temperature and decreasing total flow rate.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.277-277
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• 2011

디스플레이의 기술발전에 의해 대면적 고해상도의 LCD가 제작되어 왔다. 이에 따라 LCD 점등검사를 위한 Probe Unit의 기술 또한 급속도로 발전하고 있다. 고해상도에 따라 TFT LCD pad가 미세피치화 되어가고 있으며, panel의 검사를 위한 Probe 또한 30 um 이하의 초미세피치를 요구하고 있다. 따라서, 초미세 pitch의 LCD panel의 점등검사를 위한 Probe Unit의 개발이 시급하가. 본 연구에서는 30 um 이하의 미세피치의 Probe block을 위한 Slit wafer의 식각 공정 조건을 연구하였다. Si 공정에서 식각율과 식각깊이에 따른 profile angle의 목표를 설정하고, 식각조건에 따라 이 두 값의 변화를 관측하였다. 식각실험으로 Si DRIE 장비를 이용하여, chamber 압력, cycle time, gas flow, Oxygen의 조건에 따라 각각의 단면 및 표면을 SEM 관측을 통해 최적의 식각 조건을 찾고자 하였다. 식각율은 5um/min 이상, profile angle은 $90{\pm}1^{\circ}$의 값을 목표로 하였다. 이 때 최적의 식각조건은 Etching : SF6 400 sccm, 10.4 sec, passivation : C4F8 400 sccm, 4 sec의 조건이었으며, 식각공정의 Coil power는 2,600 W이었다. 이러한 조건의 공정으로 6 inch Si wafer에 공정한 결과 균일한 식각율 및 profile angle 값을 보였으며, oxygen gas를 미량 유입함으로써 식각율이 균일해짐을 알 수 있었다. 결론적으로 최적의 Slit wafer 식각 조건을 확립함으로써 Probe Unit을 위한 Pin 삽입공정 또한 수율 향상이 기대된다.

• 한국세라믹학회지
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• 제47권3호
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• pp.262-267
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• 2010

a-SiC has been thought as an ideal candidate for conventional silicon at many applications. However, the uniformity problem of deposition has been a obstacle for conventional use of a-SiC:H films. a-SiC:H films were deposited on (100) silicon wafer by RPECVD system in various temperature. HMDS and $H_2$ gas were used as a precursor and a carrier gas, respectively. The flow rate of HMDS source and $C_2H_2$ dilution gas was fixed in order to study the carbon effect on the film stoichiometric and bonding properties. The plasma power varied from 200 to 400W. We used three types of source delivery line to control the uniformity and film properties of deposited film. We showed that the change of source delivery line has effect on the film uniformity of deposited film and this change of line did not affect on film properties. Also, the change of deposition conditions has effect on the film uniformity.

• 한국전기전자재료학회논문지
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• 제21권3호
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• pp.222-226
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• 2008

With different seed adhesion methods, we obtained two different aspects with or without micro-bubble in the interface between a seed and a dense graphite seed holder. To improve the quality of SiC wafer, we introduced a sucrose caramelizing step at the seed adhesion using the sucrose, The n-type 2 inch single crystal exhibiting the polytype of 6H-SiC were successfully fabricated and carrier concentration levels of about $10^{16}/cm^3$ was determined from Hall measurements, As compared to the characteristics of SiC crystal grown with micro-bubble in the interface between the seed and the dense graphite seed holder, the SiC crystal grown without micro-bubble definitely exhibited lower resistivity, lower micropipe density and higher mobility relatively.