• BMB Reports
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• v.39 no.2
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• pp.167-170
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• 2006

Bovine adenosine deaminase undergoes a nondenaturational conformational change at $29^{\circ}C$ upon heating which is characterized by a large increase in heat capacity. We have determined the transition state thermodynamics of the conformational change using a novel application of differential scanning calorimetry (DSC) which employs very slow scan rates. DSC scans at the conventional, and arbitrary, scan rate of $1^{\circ}C/min$ show no evidence of the transition. Scan rates from 0.030 to $0.20^{\circ}C/min$ reveal the transition indicating it is under kinetic control. The transition temperature $T_t$ and the transition temperature interval ${\Delta}T$ increase with scan rate. A first order rate constant $k_1$ is calculated at each $T_t$ from $k_1\;=\;r_{scan}/{\Delta}T$, where $r_{scan}$ is the scan rate, and an Arrhenius plot is constructed. Standard transition state analysis reveals an activation free energy ${\Delta}G^{\neq}$ of 88.1 kJ/mole and suggests that the conformational change has an unfolding quality that appears to be on the direct path to the physiological-temperature conformer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.345-355
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• 2014

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

• Journal of the Korean Society for Nondestructive Testing
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• v.13 no.3
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• pp.7-13
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• 1993

Fracture behavior of pre-cracked compact tension specimens made of AISI 4130 steel was investigated using acoustic emission (AE) and ultrasonic C-scan measurements. While each specimen was loaded up to a certain level, various acoustic emission parameters were recorded together with the crack opening displacement (COD). An elastic-plastic finite element analysis was performed to calculate COD and the damage (plastic) zone size ahead of crack tip. Ultrasonic C-scans, in a pulse-echo, immersion mode, were done for mapping the damage zone size. The agreement between the finite element results and the measured COD was satisfactory. Based on AE results, the test specimens were found to show ductile behavior. The slope of the total ringdown counts vs. COD curve was useful to determine the crack initiation. The preliminary C-scan images showed evidence of changes in the amplitude of ultrasonic signal in the damaged region, and the shape and size of the damage zone matched qualitatively with the finite element results. A further work on the damage zone sizing was also pointed out.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.286-292
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• 2012

Scan techniques are almost mandatorily adopted in designing current System-on-a-Chip (SoC) to enhance testability, but inadvertently secret keys can be stolen through the scan test channels of crypto SoCs. An efficient scan design technique is proposed in this paper to protect the secret key of an Advanced Encryption Standard (AES) core embedded in an SoC. A new instruction is added to IEEE 1149.1 boundary scan to use a fake key instead of user key, in which the fake key is chosen with meticulous care to improve the testability as well. Our approach can be implemented as user defined logic with conventional boundary scan design, hence no modification is necessary to any crypto IP core. Conformance to the IEEE 1149.1 standards is completely preserved while yielding better performance of area, power, and fault coverage with highly robust protection of the secret user key.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.49-58
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• 1998

In this paper, we report new algorithms to select scan flip-flops for the no holding partial scan test method. The no holding partial scan test method is identical to the full scan test method except that some flip-flops are left unscanned. This test method does not hold scanned or unscanned flip-flops while shifting in test vectors, or applying them, or shifting out test results. The proposed algorithm allows a large number of flip-flops to be left unscanned while maintaining almost the complete full scan fault coverage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.1-15
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• 1998

In this paper, we propose a partial scan test method which can be applied to large VLSI designs. In this method, it is not necessary to hold neither scanned nor unscanned flip-flops during scan in, test application,or scan out. This test method requires almost identical design for testability modification and test wave form when compared to the full scan test method, and the method is applicable to large VLSI chips. The well known FAN algorithm has been modified to devise to sequential ATPG algorithm which is effective for the proposed test method. In addition, a partial scan algorithm which is effective for the proposed test method. In addition, a partial algorithm determined a maximal set of flip-flops which gives high fault coverage when they are unselected. The experimental resutls show that the proposed method allow as large as 20% flip-flops to remain unscanned without much decrease in the full scan fault coverage.

• The Journal of the Korea Contents Association
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• v.5 no.1
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• pp.229-236
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• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.77-86
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• 2010

This paper presents an efficient secure scan design technique which is based on a fake key and IEEE 1149.1 instruction to protect secret key from scan-based side channel attack for an Advanced Encryption Standard (AES) core embedded on an System-on-a-Chip (SoC). Our proposed secure scan design technique can be applied to crypto IP core which is optimized for applications without the IP core modification. The IEEE 1149.1 standard is kept, and low area, low power consumption, very robust secret-key protection and high fault coverage can be achieved compared to the existing methods.

• Proceedings of the KOSOMBE Conference
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• v.1996 no.11
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• pp.157-160
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• 1996

In this paper, reconstruction algorithms of spiral scan imaging which has been used for ultra fast magnetic resonance imaging have been reviewed, and some simulation results using two different algorithms are reported. Since the trajectory of the spiral scan in k-space is the spiral, reconstruction of the spiral scan is not as straight forward as that used in Fourier imaging technique where the sampling points are usually on the rectangular grids. Originally the reconstruction of the spiral scan imaging was based on the convolution backprojection algorithm modified with a shift term, however, some other reconstruction techniques have also been tried by remapping sampling points from spiral trajectory to Cartesian grids. Some experimental aspects of MR spiral scan imaging will also be addressed.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.7
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• pp.32-39
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• 1999

Digital signal processor (DSP) is used to obtain the peak value and the time difference of ultrasonic signals, to make digital filter, and to derive mathematical transformation from analog circuit. In this study, C-scan system and control program have been developed to high speed data acquisition. This system consists of signal processing parts (DSP, oscilloscope, pulser/receiver, digitizer), scanner, and control program. The developed system has been applied to a practical ultrasonic testing in overlay weld, and demonstrated high speed with precision