• Title/Summary/Keyword: C-FLIP

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Impact of External Temperature Environment on Large FCBGA Sn-Ag-Cu Solder Interconnect Board Level Mechanical Shock Performance

  • Lee, Tae-Kyu
    • Journal of Welding and Joining
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    • v.32 no.3
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    • pp.53-59
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    • 2014
  • The mechanical stability of solder joints in electronic devices with Sn-Ag-Cu is a continuous issue since the material was applied to the industry. Various shock test methods were developed and standardized tests are used in the industry worldwide. Although it is applied for several years, the detailed mechanism of the shock induced failure mechanism is still under investigation. In this study, the effect of external temperature was observed on large Flip-chip BGA components. The weight and size of the large package produced a high strain region near the corner of the component and thus show full fracture at around 200G level shock input. The shock performance at elevated temperature, at $100^{\circ}C$ showed degradation based on board pad designs. The failure mode and potential failure mechanisms are discussed.

Fabrication of 1-${\mu}m$ channel length OTFTs by microcontact printing

  • Shin, Hong-Sik;Baek, Kyu-Ha;Yun, Ho-Jin;Ham, Yong-Hyun;Park, Kun-Sik;Lee, Ga-Won;Lee, Hi-Deok;Wang, Jin-Suk;Lee, Ki-Jun;Do, Lee-Mi
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.1118-1121
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    • 2009
  • We have fabricated inverted staggered pentacene Thin Film Transistor (TFT) with 1-${\mu}m$ channel length by micro contact printing (${\mu}$-CP) method. Patterning of micro-scale source/drain electrodes without etching was successfully achieved using silver nano particle ink, Polydimethylsiloxane (PDMS) stamp and FC-150 flip chip aligner-bonder. Sheet resistance of the printed Ag nano particle films were effectively reduced by two step annealing at $180^{\circ}C$.

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A study on the microcontroller-based color control circuit for high brightness LEDs (마이크로컨트롤러를 이용한 고휘도 LED의 광색가변 회로에 관한 연구)

  • Yu, Yong-Su;Song, Sang-Bin;Gwark, Jae-Young;Yeo, In-Seon
    • Proceedings of the KIEE Conference
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    • 2000.07b
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    • pp.1342-1344
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    • 2000
  • This paper presents a microcontroller-based control circuit for color variation of high brightness RGB LEDs in $8{\times}8$ matrix array. The control circuit is comprised of an AT89C52 chip, D Flip-flops, and transistors for switching, and is used to adjust the number of LEDs operated for color variation. For a stable operation, it is required that the input current to each LED should be maintained to a normal value irrespective of the number of LEDs operated.

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Synthesis and X-ray Crystallographic Characterization of p-Diacetylcalix[4]arene

  • Young Ja Park;Kwanghyun No;Jung Mi Shin
    • Bulletin of the Korean Chemical Society
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    • v.12 no.5
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    • pp.525-529
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    • 1991
  • A simple route is described for the selective functionalization of calixarene at the para positions of phenyl rings. Calix[4]arene tetraacetate 2, obtained from the treatment of calix[4]arene with acetic anhydride, undergoes Fries rearrangement to yield the diametrically para substituted p-diacetylcalix[4]arene 3 in 80% yield. The crystal and molecular strucutre has been determined by X-ray diffraction method. The crystals are orthorhombic, space group Pna21, with a = 11.121 (3), b = 10.374 (3), c = 21.690 (6) $\AA$ and Z = 4. The structure was solved by direct method and refined by full-matrix least-squares methods to final R of 0.036 for 1795 observed reflections. Each hydroxyl hydrogen atom is disordered over two positions. The macrocycle exists in the cone conformation which is determined by the strong circular intramolecular flip-flop type hydrogen bonds of phenolic OH, while crystal packing effects of the diametrically para-acetyl substituents seem to be responsible for the distortion of the cone conformation.

A SDL Hardware Compiler for VLSI Logic Design Automation (VLSI의 논리설계 자동화를 위한 SDL 하드웨어 컴파일러)

  • Cho, Joung Hwee;Chong, Jong Wha
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.3
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    • pp.327-339
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    • 1986
  • In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

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Design of a 2.5GHz CMOS PLL Frequency Synthesizer Using a High-Speed Low-Power Prescaler (고속 저전력 프리스케일러를 사용한 2.5GHz CMOS PLL 주파수합성기 설계)

  • Kang, K.S.;Oh, G.C.;Lee, J.K.;Park, J.T.;Yu, C.G.
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.877-880
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    • 2005
  • This paper describes a PLL frequency synthesizer for wireless LNA applications. The design is focused mainly on low-power and low-phase noise characteristics. A 128/129 dual-modulus prescaler has been designed using the proposed TSPC D flip-flops for high-speed operation and low-power consumption The designed synthesizer includes all building blocks for elimination of external components, other than the crystal. Its operating frequency can be programmed by external data. The frequency synthesizer has been designed using a $0.25{\mu}m$ CMOS process parameters. It operates in the frequency range of 2GHz to 3GHz and consumes 3.2mA at 2.5GHz from a 2.5V supply.

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비전도성 에폭시를 사용한 RF-MEMS 소자의 웨이퍼 레벨 밀봉 실장 특성

  • 박윤권;이덕중;박흥우;송인상;박정호;김철주;주병권
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2001.11a
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    • pp.129-133
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    • 2001
  • In this paper, hermetic sealing was studied fur wafer level packaging of the MEMS devices. With the flip-chip bonding method, this B-stage epoxy sealing will be profit to MEMS device sealing and further more RF-MEMS device sealing. B-stage epoxy can be cured 2-step and hermetic sealing can be obtained. After defining $500{\mu}{\textrm}{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was then aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line were maintained during the sealing process. The height of the seal-line was controlled within $\pm0.6${\mu}{\textrm}{m}$ and the strength was measured to about 20MPa by pull test. The leak rate of the epoxy was about $10^7$ cc/sec from the leak test.

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Shear Strength and Aging Characteristics in Solder Bumps for High Reliability Optical Module (고신뢰성 광모듈을 위한 솔더 범프의 전단강도와 시효 특성)

  • 유정희
    • Journal of Welding and Joining
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    • v.21 no.2
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    • pp.97-101
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    • 2003
  • The change of microstructures in the base metal during transient liquid phase bonding process of directionally Ni base superalloy, GID-111 was investigated. Bonds were fabricated using a series of holding times(0~7.2ks) at three different temperatures. The flip chip bonding utilizing self-aligning characteristic of solder becomes mandatory to meet tolerances for the optical device. In this paper, a parametric study of aging condition and pad size of samples was evaluated. A TiW/Cu/electroplated Cu UBM structure was selected and the samples were aging treated to analyze the effect of intermetallic compounds with the time variations. An FIB technique was applied to the preparation of samples for TEM observations. An FIB technique is very useful to prepare TEM thin foil specimens from the solder joint interface. After aging treatment, the tendency to decrease in shear strength was measured and the structure of the solder and the UBM was observed by using SEM, TEM and EDS. As a result, the shear strength was decreased of about 21% in the 100${\mu}{\textrm}{m}$ sample at 17$0^{\circ}C$ aging compared with the maximum shear strength of the sample with the same pad size. In the case of the 12$0^{\circ}C$ aging treatment, 18% of decrease in shear strength was measured at the 100${\mu}{\textrm}{m}$ pad size sample. An intermetallic compound of Cu6Sn5 and Cu3Sn were also observed through the TEM measurement by using.

Aging Characteristics of Solder bump Joint for High Reliability Optical module (광모듈 솔더 접합부의 시효 특성에 관한 연구)

  • Kim, Nam-Kyu;Kim, Kyung-Seob;Kim, Nam-Hoon;Chang, Eui-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.05c
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    • pp.204-207
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    • 2003
  • The flip chip bonding utilizing self-aligning characteristic of solder becomes mandatory to meet to tolerances for the optical device. In this paper, a parametric study of aging condition and pad size of sample was conducted. A TiW/Cu UBM structure was adopted and sample was aging treated to analyze the effect of intermetallic compound with time variation. After aging treatment, the tendency to decrease in shear strength was measured and the structure of the fine joint area was observed by using SEM, TEM and EDS. In result, the shear strength was decreased of about 20% in the $100{\mu}m$ sample at $170^{\circ}C$ aging compared with the maximum shear strength of same pad size sample. In the case of the $120^{\circ}C$ aging treatment, 17% of decrease in shear strength was measured at the $100{\mu}m$ pad size sample. Also, intremetallic compound of $Cu_6Sn_5$ and $Cu_3Sn$ were observed through the TEM measurement by using an FIB technique that is very useful to prepare TEM thin foil specimens from the solder joint interface.

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