• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.69-76
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• 2007

A new circuit design for Bus-Invert Coding is presented in this paper. The new scheme sends the coding information through the bus-lines instead of the invert-line which has been used conventionally for many types of Bus-Invert algorithms. By employing a newly developed bus-driver called Flip-Driver and a selection circuit, it not only removes the invert-line but suppresses the additional bus-transitions in sending coding information. It is verified by simulations that the efficiency of various Bus-Invert algorithms is increased about 40% to 100% by employing the new design.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.436-442
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• 2014

A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1081-1084
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• 1998

In this paper, we propose the bus coding technique for low power consumption. For CMOS circuit most power is dissipated as dynamic power for charging and discharging node capacitances.Though the I/O and bus are likely to have the very large capacitances associated with them and dissipate much of the power dissipated by an IC, they have little beenthe special target for power reduction. The conventional Bus-Invert coding method can't decrease the peak power dissipation by 50% because the additional invert signal line can invoke a transition at the time when Bus-Invert coding isn't used to code original bus data. The proposed technique always constraints the Hamming distance between data transferred sequentially to be below the half of the bus width, and thus decrease the I/O peak power dissipation and the I/O average power dissipation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.23-30
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• 1998

We present a partial bus-invert coding scheme for system-level power optimization. In the proposed scheme, we select a sub-group of bus lines involved in bus encoding to avoid unnecessary inversion of bus lines not in the sub-group thereby reducing the total number of bus transitions. We propose a heuristic algorithm that selects the sub-group of bus lines for bus encoding. Experiments on benchmark examples indicate that the partial bus-invert coding reduces the total bus transitions by 62.6% on the average, compared to that of the unencoded patterns. We also compare the performance of the proposed heuristic algorithm with that of simulated annealing, which shows that it is highly efficient.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.71-79
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• 2004

Packet-type data transmission is characterized by the continuous transmission of massive data with relatively constant rate. In such transmission, the dynamic power consumed on buses is influenced by the sequence of transmitted data. A new coding scheme called Sequence-Switch Coding (SSC) is proposed in this paper. SSC reduces the number of bus transitions in the transmission of packet-type data by changing the sending order of the data. Some simple algorithms are presented, In. The simulation results show that SSC outperforms the well-known Bus-Invert Coding with these algorithms. SSC is not a specific algerian but a method to reduce the number of bus-transitions. There could be lots of algorithms for realizing SSC. The variety of SSC algorithms provides circuit designers a wide range of trade-off between performance and circuit complexity.

• 전자공학회논문지 IE
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• v.45 no.3
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• pp.5-12
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• 2008

We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.1_2
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• pp.52-57
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• 2001

이 논문에서는 우리는 버스에서의 연속된 데이터 전송 시 발생하는 데이터 값의 천이를 줄이는 새로운 버스-인버트 코딩에 적용 된 것과는 달리, 우리의 기법은 다양한 버스 분할을 시도하여, 각 분할에 독립적으로 버스-인버트 코딩을 적용하여 전체의 데이터 값 천이를 최소화하고자 한다. 실제 회로를 통한 실험에서 기존의 버스-인버트 코딩과 비교하여 우리의 제안한 기법은 데이터 값의 천이를 전체적으로 10%-50% 수준으로 줄일 수 있음을 보여 준다.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.27-29
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• 2000

버스-인버트 코딩 기법은 버스에서의 연속된 데이터 전송시 발생하는 데이터 값의 천이를 줄이는 기법이다. 기존의 방식에서는 전체버스 라인이나 그중의 한 일부분만에 버스-인터트 코딩을 적용했었던 것과는 달리, 우리의 기법은 버스 라인들을 몇 개의 묶음으로 분할하여, 각 묶음에 대해 독립적으로 버스-인버트 코딩을 적용하여 데이터 값의 천이를 최소화 하려고 한다. 실험을 통해서 우리의 기법은 데이터 값의 천이를 전체적으로 10-50% 감소시킬수 있음을 나타났다.