• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.523-530
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• 2005

When a PCI 2.2 bus master requests data using Memory Read command, a target device may hold PCI bus without data to be transferred for long time because a target device needs time to prepare data infernally. Because the usage efficiency of the PCI bus and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the system performance. But the mechanism cann't fully improve performance because a target device doesn't know the exact size of prefetched data. In the previous work, we propose a new method called Prefetch Request when a bus master intends to read data from the target device. In this paper, we design PCI 2.2 controller and local device that support the proposed method. The designed PCI 2.2 controller has simple local interface and it is used to convert the PCI protocol into the local protocol. So the typical users, who don't know the PCI protocol, can easily design the PCI target device using the proposed PCI controller. We propose the basic behavioral verification, hardware design verification, and random test verification to verify the designed hardware. We also build the test bench and define assembler instructions. And we propose random testing environment, which consist of reference model, random generator ,and compare engine, to efficiently verify corner case. This verification environment is excellent to find error which is not detected by general test vector. Also, the simulation under the proposed test environment shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about $9\%$.

• Transactions of the Korean Society of Automotive Engineers
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• v.10 no.4
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• pp.175-180
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• 2002

In order to satisfy the requirements of time reduction and cost saving for development of electronic control systems(ECU) in automotive industry, the applications of a standardized real-time operating system(RTOS) and a communication protocol to ECUs are increased. In this study, a body control module(BCM) that employs OSEK/VDX(open system and corresponding interfaces for automotive electronics/vehicle distributed executive) OS tour the RTOS and a controller area network(CAN) fur the communication protocol is designed, and the performances of the system are evaluated. The BCM controls doors, mirrors, and windows of the vehicle through the in-vehicle network. To identify all the transmitted and received control messages, a PC connected with the CAN communication protocol behaves as a CAN bus emulator. The control system based upon in-vehicle network improves the system stability and reduces the number of wiring harness. Furthermore it is easy to maintain and simple to add new features because the system is designed based on the standards of RTOS and communication protocol.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.2
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• pp.1-9
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• 2012

In this paper, we design and implement a DCS (Distributed Control System) based on dual field-bus for ship engine. For monitoring and controlling the condition of the ship engine, an implemented DCS is consisted of two-tier communication structure by using CAN (Controller Area Network) and MODBUS protocols. The first-tier is consisted of CAN protocol for sharing the condition of the ship engine by each implemented monitoring system. By using MODBUS protocol, the second-tier is used for communicating the monitoring data from an implemented DCS to AMS(Alarm Monitoring System). We verified and tested our scheme and implemented DCS by KR (Korea Register) technical rules through experimental tests.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.8
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• pp.2436-2448
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• 1996

This paper presents the development of three types of network performance manager for IEEE 802.4 token bus networks that are a part of Manufacturing Automation Protocol(MAP). The performance managers attempt to keep the average data latency below a certain level specified for each priority class. All of the three performance managers are based on a set of fuzzy rules incorporating the knowledge on the relationship between data latency and parameters of the priority mechanism. These Fuzzy Network Performance Managers(FNPMs) have been evaluated via discrete event simulation to demonstrate their efficacy.

• Journal of IKEEE
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• v.28 no.1
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• pp.116-122
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• 2024

AMBA AHB-Lite bus is widely used in on-chip bus protocol for low-power and cost-effective SoC. However, it lacks built-in error detection and correction for end-to-end data integrity. This can lead to data corruption and system instability, particularly in harsh environments like automotive applications. To mitigate this problem, this paper proposes the application of SEC-DED (Single Error Correction-Double Error Detection) to AMBA AHB-Lite bus. It aims not only to detect errors in real-time but also to correct them, thereby enhancing end-to-end data integrity. Simulation results demonstrate real-time error detection and correction when errors occur, which bolsters end-to-end data integrity of automotive on-chip bus.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.33-44
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• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.

• The Transactions of the Korea Information Processing Society
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• v.1 no.2
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• pp.263-271
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• 1994

Automation of production in modern manufacturing is based on the integration of the various stage of production process by means of processing system. Information processing and network interface are of fundamental importance in programmable device in industrial automation, as they essential in order to active integration in production lines. In this paper, TBC(token bus controller) in the Mini-MAP board performs the function of the MAC sublayer, The LLC sublayer is implemented according to the specification of Class 3 that includes Type 1 and 3. And the MMS services are designed within the scope of implementation MAP 3.0 All the softwares are implemented under the real time executive for real time application of the Mini-MAP and they are loaded into PROMs at the network board. We tested the LLC functions to make use of a protocol analyzer for the token bus protocol. Also the MMS conformance test was carried out by exchanging primitives between a model system(including NIU) and a MMS product that had already passed the conformance the conformance test based on measurement method of network analysis.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1610-1618
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• 2014

Wearable computer systems can use the wireless universal serial bus (WUSB) that refers to USB technology that is merged with WiMedia PHY/MAC technical specifications. In this paper, we focus on an integrated system of the wireless USB over the IEEE 802.15.6 wireless body area networks (WBAN) for wireless wearable computer systems supporting U-health services. And a communication structure that performs the hibernation for low power consumption is proposed for WUSB over IEEE 802.15.6 hierarchical protocol. In the proposed hibernation mechanisms, WUSB communications are permitted at each m-periodic inactive periods of WBAN superframes by using the WBAN information of Wakeup Period and Wakeup Phase message fields. In our performance evaluations, performances according to amount of WUSB traffic and Wakeup Periods are analyzed respectively to evaluate the effectiveness of proposed hibernation structure in WUSB over IEEE 802.15.6.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.687-689
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• 2004

As using of network increases rapidly, performance of system has been deteriorating because of the overhead and bottleneck. Nowadays, High speed I/O network standard, that is a sort of PCI Express, HyperTransport, InfiniBand, and so on, has come out to improve the limites of traditional I/O bus. The InfiniBand Architecture(IBA) provides some protocols to service the applications such as SDP, SRP and IPoIB. In our paper, We explain the architecture of IPoIB (IP over InfiniBand) and its features in channel based I/O network. And so we provide a performance evaluation result of IPoIB which is compared with current network protocol. Our experimental results also show that IPoIB is batter than TCP/IP protocol. For this test, We use the dual processor server systems and Linux Redhat 9.0 operating system.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.77-81
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• 2006

Because of the rapid increasing of network user, there are some problems to tolerate the network overhead. Recently, the research and technology of the user-level for high performance and low latency than TCP/IP which relied upon the kernel for processing the messages. For example, there is an Infiniband technology. The Infiniband Trade Association (IBTA) has been proposed as an industry standard for both communication between processing node and I/O devices and for inter-processor communication. It replaces the traditional bus-based interconnect with a switch-based network for connecting processing node and I/O devices. Also Infiniband uses RDMA (Remote DMA) for low latency of CPU and OS to communicate between Remote nodes. In this paper, we develop the SRP (SCSI RDMA Protocol) which is Storage Access Protocol on Infiniband network. And will compare to FC (Fibre Channle) based I-SCSI (Internet SCSI) that it is used to access storage on Etherent Fabric.