• 전자공학회논문지B
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• 제33B권9호
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• pp.70-79
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• 1996

Block data transfer poses a serious problem is a pipelined bus where each data transfer step is pipelined. In this paper, we describe the design and implementation of a variable data block transfer protocol for a pipelined bus of a shared-memory multiprocessor. The proposed method maintains compatibility with the existing protocol for the pipelined bus and ensures fairness and effectiveness by preventing starvation. We present flow charts of requester and responder during a block transfer in the pipelined bus that uses the proposed protocol. The proposed protocol was implemented for the TICOM-III HiPi+Bus.

• 전자공학회논문지A
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• 제33A권7호
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• pp.76-91
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• 1996

In this paper, we proposed the new medium access control protocol for the virtual token bus netowrk. The network is applied to inter-processor communication network of large capacity digital switching system and digital mobile system with distributed control architecture. in the virtual token bus netowrk, the existing medium access control protocols hav ea switchove rtime overhead when traffic load is light or asymmetric according ot arbitration address of node that has message to send. The proposed protocol optimized average message delay using cyclic bus access chain to exclude switchover time of node that do not have message to send. Therefore it enhanced bus tuilization and average message delay that degrades the performance of real time communication netowrks. It showed that the proposed protocol is more enhacned than virtual token medium access control protocol and virtual token medium access control protocol iwth reservation through performance analysis.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2011년도 정기총회 및 추계학술대회 논문집
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• pp.2782-2786
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• 2011

In this paper a protocol design for bus network communication between onboard signalling system and MMI(Man Machine Interface) will be presented and illustrated. Recently, many onboard signailling systems adopt hot standby for safety reasons. Hot standby is a method of redundancy in which the primary and secondary systems run simultaneously. It is convenient to use bus network(bus topology) in a hot standby system for communication between onboard signalling system and MMI. Because bus network is the simplest way to connect multiple clients such as onboard signalling system, MMI and etc. However, there are many problems when two clients want to transmit at the same time on the same bus. A effective protocol is necessary to solve that problems. We will describes protocol design which is useful when onboard signalling systems and MMIs are connected via RS485(Bus Network).

• 전기전자학회논문지
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• 제8권2호
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• pp.207-215
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• 2004

계층버스 다중처리기 시스템에서 캐시 일관성 프로토콜은 시스템 성능에 영향을 준다. 특정 캐시 일관성 프로토콜 하에서 시스템의 성능은 버스의 대역폭 및 메모리크기, 메모리 블록의 크기에 따라 영향을 받는다. 따라서 시스템 성능에 영향을 미치는 요소들에 대한 민감도 분석이 필요하다. 본 논문에서는 계층버스 다중처리기에 캐시 일관성 프로토콜을 적용하고, 프로토콜에서 정의된 상태가 나타날 확률을 구하였다. 구해진 확률값을 분석적 모델에 적용하여 시뮬레이션을 하였다. 그리고 시뮬레이션 결과를 기반으로 시스템의 성능에 영향을 미치는 요소에 대한 민감도 분석을 하였다.

• 대한산업공학회지
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• 제41권1호
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• pp.74-78
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• 2015

A bus seat is required to be ergonomically designed in terms of its shape and physical properties to increase seating comfort. The present study is intended to develop a systematic bus seat evaluation protocol based on seating comfort. A total of 48 participants evaluated 12 parts (seat belt, recliner, armrest, headrest, upper-back support, lumbar support, seatback bolster, seatback overall, hip support, thigh support, seatpan bolster, and seatpan overall) of 12 bus seats with 17 subjective comfort measures (e.g., convenience of control, suitability of size, and overall comfort). Lastly, ergonomic features of shape and physical properties of each seat part were identified based on the subject evaluation analysis results. The developed bus seat evaluation protocol can be applied to evaluate various types of seats.

• 한국정보과학회논문지:시스템및이론
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• 제33권9호
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• pp.699-708
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• 2006

버스 분할 기법은 통신이 많은 모듈들을 가까이 배치하고 필요한 버스 단편만 사용함으로 버스 에너지 소비를 줄인다. 그러나 MPSoC와 같은 다중 프로세서 플랫폼에서는 캐시 일관성을 유지하기 위하여 모든 프로세서에서 버스 트랜잭션을 알아야 하므로, 기존의 버스 분할 기법을 적용할 수 없다. 본 논문에서는 공유 메모리 기반의 MPSoC 플랫폼에서 버스 에너지를 절감시키기 위한 버스 분할 기법을 제안한다. 제안된 버스 분할 기법은 비 공유 메모리와 공유 메모리의 버스를 분할함으로써, 캐시 일관성을 유지하며 비 공유 메모리를 참조할 때 소비하는 버스 에너지를 최소화시킨다. 또한, 태스크별 버스 트랜잭션 횟수를 기반하여 태스크를 할당함으로써, 공유 메모리를 참조할 때 소비하는 버스 에너지를 절감시키는 캐시 일관성을 고려한 태스크 할당 기법을 제안한다. 시뮬레이션을 통한 실험에서 제안된 버스 분할 기법은 비 공유 메모리 참조시의 버스 에너지를 최대 83%까지 절감시키며, 태스크 할당 알고리즘은 공유 메모리 참조시의 버스 에너지를 최대 36%까지 절감시키는 효과가 있음을 보여준다. 그럼으로 다중 프로세서 시스템에서도 버스 분할 기법을 적용하여 버스 에너지 절감 효과를 볼 수 있으며, 캐시 일관성을 고려한 태스크 할당 기법을 통해 추가적으로 버스 에너지를 절감할 수 있음을 보여준다.

• 전기학회논문지P
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• 제62권1호
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• pp.23-29
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• 2013

TCN(train communication network) standard was approved in 1999 by the IEC (IEC 61375-1) and IEEE (IEEE 1473-T) organizations to warrant a reliable train and equipment interoperability. TCN defines the set of communication vehicle buses and train buses. The MVB(multifunction vehicle bus) defines the data communication interface of equipment located in a vehicle and the WTB(wire train bus) defines the data communication interface between vehicles. The WTB and each MVB will be connected over a node acting as gateway. Also, to support applications demanding a high reliability, the standard defines a redundancy scheme in which the bus may be double-line and redundant-node implemented. In this paper we have presented protocol analysis platform for the WTB redundancy which is part of TCN system, to verify communication state of high-speed trains. As a confirmation of its validity, the technology described in this paper has been successfully applied to state monitoring and protocol verification of redundancy WTB based on TCN.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.333-336
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• 2002

This paper purpose design and implementation of system bus for the effective interconnection between peripheral device and 32-bit microprocessor. The designed system bus support general bus protocol. Also, it is optimized for 32-bit microprocessor. It is divided into two system. high performance system bus and Peripheral system bus.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.535-536
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• 2006

In the embedded system, external device interface that operates serial protocol with lower speed than the general computers is used commonly. This paper describes I2C bus protocol that is a bi-directional serial bus with a two-pin interface. The I2C bus requires a minimum amount of hardware to relay status and reliability information concerning the processor subsystem to an external device.