• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.9
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• pp.70-79
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• 1996

Block data transfer poses a serious problem is a pipelined bus where each data transfer step is pipelined. In this paper, we describe the design and implementation of a variable data block transfer protocol for a pipelined bus of a shared-memory multiprocessor. The proposed method maintains compatibility with the existing protocol for the pipelined bus and ensures fairness and effectiveness by preventing starvation. We present flow charts of requester and responder during a block transfer in the pipelined bus that uses the proposed protocol. The proposed protocol was implemented for the TICOM-III HiPi+Bus.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.76-91
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• 1996

In this paper, we proposed the new medium access control protocol for the virtual token bus netowrk. The network is applied to inter-processor communication network of large capacity digital switching system and digital mobile system with distributed control architecture. in the virtual token bus netowrk, the existing medium access control protocols hav ea switchove rtime overhead when traffic load is light or asymmetric according ot arbitration address of node that has message to send. The proposed protocol optimized average message delay using cyclic bus access chain to exclude switchover time of node that do not have message to send. Therefore it enhanced bus tuilization and average message delay that degrades the performance of real time communication netowrks. It showed that the proposed protocol is more enhacned than virtual token medium access control protocol and virtual token medium access control protocol iwth reservation through performance analysis.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• Proceedings of the KSR Conference
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• 2011.10a
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• pp.2782-2786
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• 2011

In this paper a protocol design for bus network communication between onboard signalling system and MMI(Man Machine Interface) will be presented and illustrated. Recently, many onboard signailling systems adopt hot standby for safety reasons. Hot standby is a method of redundancy in which the primary and secondary systems run simultaneously. It is convenient to use bus network(bus topology) in a hot standby system for communication between onboard signalling system and MMI. Because bus network is the simplest way to connect multiple clients such as onboard signalling system, MMI and etc. However, there are many problems when two clients want to transmit at the same time on the same bus. A effective protocol is necessary to solve that problems. We will describes protocol design which is useful when onboard signalling systems and MMIs are connected via RS485(Bus Network).

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.207-215
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• 2004

In a hierarchical-bus multiprocessor system, cache coherence protocol has effect on system performance. Under a particular cache coherence protocol, system performance can be affected by bus bandwidth, memory size, and memory block size. Therefore sensitivity analysis is necessary for the part of multiprocessor system. In this paper, we set up cache coherence protocol for hierarchical-bus multiprocessor system, and compute probability of state of protocol, and analyze sensitivity for part of system by simulation.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.1
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• pp.74-78
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• 2015

A bus seat is required to be ergonomically designed in terms of its shape and physical properties to increase seating comfort. The present study is intended to develop a systematic bus seat evaluation protocol based on seating comfort. A total of 48 participants evaluated 12 parts (seat belt, recliner, armrest, headrest, upper-back support, lumbar support, seatback bolster, seatback overall, hip support, thigh support, seatpan bolster, and seatpan overall) of 12 bus seats with 17 subjective comfort measures (e.g., convenience of control, suitability of size, and overall comfort). Lastly, ergonomic features of shape and physical properties of each seat part were identified based on the subject evaluation analysis results. The developed bus seat evaluation protocol can be applied to evaluate various types of seats.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.699-708
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• 2006

Bus splitting technique reduces bus energy by placing modules with frequent communications closely and using necessary bus segments in communications. But, previous bus splitting techniques can not be used in MPSoC platform, because it uses cache coherency protocol and all processors should be able to see the bus transactions. In this paper, we propose a bus splitting technique for MPSoC platform to reduce bus energy. The proposed technique divides a bus into several bus segments, some for private memory and others for shared memory. So, it minimizes the bus energy consumed in private memory accesses without producing cache coherency problem. We also propose a task allocation technique considering cache coherency protocol. It allocates tasks into processors according to the numbers of bus transactions and cache coherence protocol, and reduces the bus energy consumption during shared memory references. The experimental results from simulations say the bus splitting technique reduces maximal 83% of the bus energy consumption by private memory accesses. Also they show the task allocation technique reduces maximal 30% of bus energy consumed in shared memory references. We can expect the bus splitting technique and the task allocation technique can be used in multiprocessor platforms to reduce bus energy without interference with cache coherency protocol.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.1
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• pp.23-29
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• 2013

TCN(train communication network) standard was approved in 1999 by the IEC (IEC 61375-1) and IEEE (IEEE 1473-T) organizations to warrant a reliable train and equipment interoperability. TCN defines the set of communication vehicle buses and train buses. The MVB(multifunction vehicle bus) defines the data communication interface of equipment located in a vehicle and the WTB(wire train bus) defines the data communication interface between vehicles. The WTB and each MVB will be connected over a node acting as gateway. Also, to support applications demanding a high reliability, the standard defines a redundancy scheme in which the bus may be double-line and redundant-node implemented. In this paper we have presented protocol analysis platform for the WTB redundancy which is part of TCN system, to verify communication state of high-speed trains. As a confirmation of its validity, the technology described in this paper has been successfully applied to state monitoring and protocol verification of redundancy WTB based on TCN.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.333-336
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• 2002

This paper purpose design and implementation of system bus for the effective interconnection between peripheral device and 32-bit microprocessor. The designed system bus support general bus protocol. Also, it is optimized for 32-bit microprocessor. It is divided into two system. high performance system bus and Peripheral system bus.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.535-536
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• 2006

In the embedded system, external device interface that operates serial protocol with lower speed than the general computers is used commonly. This paper describes I2C bus protocol that is a bi-directional serial bus with a two-pin interface. The I2C bus requires a minimum amount of hardware to relay status and reliability information concerning the processor subsystem to an external device.