• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.55 no.9
• /
• pp.351-358
• /
• 2006

In this paper, DSPOCS(Digital Switchgear-Panel Operation and Control Solution) is designed, which is the intelligent inference based operation and control solution to obtain the safety and reliability of electric power supply in substation based on IED. DSPOCS is designed as a scheduled monitoring and control task and a real-time alarm inference task, and is interlinked with BRES(Bus Reconfiguration Expert System) in the required case. The intelligent alarm inference task consists of the alarm knowledge generation part and the real-time pattern matching part. The alarm knowledge generation part generates automatically alarm knowledge from DB saves it in alarm knowledge base. On the other hand, the pattern matching part inferences the real-time event by comparing the real-time event information furnished from IEDs of substation with the patterns of the saved alarm knowledge base.; Especially, alarm knowledge base includes the knowledge patterns related with fault alarm, the overload alarm and the diagnosis alarm. In order to design the database independently in substation structure, busbar is represented as a connectivity node which makes the more generalized graph theory possible. Finally, DSPOCS is implemented in MS Visual $C^{++}$, MFC, the effectiveness and accuracy of the design is verified by simulation study to the typical distribution substation.

• Proceedings of the Safety Management and Science Conference
• /
• 2005.05a
• /
• pp.65-80
• /
• 2005

대부분의 국가들이 노선버스의 운영을 공공부문에서 담당하고 있으나 우리나라를 비롯한 일부에서만 민간이 운영하고 있어 시민들을 위한 공익성만을 추구 할 수는 없는 입장이며 노선의 선정 또한 사업자와 공공이 협의하여 시행할 수밖에 없다. 이를 개선하기 위하여 버스노선 개편, 공동배차제 등 개선방안을 많은 지자체에서 시행하였지만 시민${\cdot}$업체${\cdot}$공공부문에서의 합의 도출은 지난한 상황이며 실행력이 없는 계획이 되고 있음을 여러 사례에서 볼 수 있다. Internet등 통신기술의 급속한 발달에 따라 통신을 통한 의사표출이 자유롭고 용이해지면서 일반지자체의 경우에 전체 민원 중 교통부문이 차지하는 민원이 $50\%$를 상회하고 있으며, 교통민원 중 $45.3\%$가 노선버스의 정시성 확보 및 운전기사의 불친절, 무정차 통과 등에 관한 것으로써 시민들이 가장 알고싶어 하는 사항이 버스의 실시간 운행상황임을 알 수 있었다. 따라서 본 연구에서는 실시간 버스정보제공을 통해 노선버스 이용자들의 대기시간 감소 및 이용편의를 증진시키고, 이를 통해 승용차 이용자를 대중교통수단으로 유도하여 대중교통을 활성화시키는 버스정보시스템(BIS ; Bus Information System)을 정립하며, 충주시 교통여건을 감안한 버스정보시스템 도입전략을 수립하고, 도입에 따른 기대효과를 분석하여 합리적이고 효과적으로 적용할 수 있는 지방자치단체 특히 충주시의 지능형 교통정보 시스템을 마련하는데 그 목적이 있다.

• Journal of KIISE:Computing Practices and Letters
• /
• v.5 no.3
• /
• pp.351-359
• /
• 1999

최근 IEEE-1394 직렬버스는 컴퓨터와 가전기기가 결합된 차세대 가정 자동화를 위한 통신 기술로 주목받고 있다. 본 논문은 이러한 1394 버스에서 사용할 수 있는 PC용 화상 전화시스템 (VPS) 구현에 대한 내용을 기술한 것이다. 개발된 화상 전화 시스템은 기본적으로 고품질의 오디오와 비디오를 실시간으로 전송할수 있으며 온라인 문자정보를 교환을 위한 채팅기능과 사용중 문서나 이미지를 전달할 수 있는 고속 파일 전송 기능을 부가적으로 제공하고 있다. VPS는 내부적으로 실시간 처리기능이 없는 일반 PC 운영체제에서 실시간 전송이 가능한 1394 버스를 사용할 때 컴퓨터 시스템이 불안정해지는 문제를 피하고 손실에 민감한 오디오를 보호하기 위하여 부하에 따라 비디오 처리를 조절하는 비대칭적 버퍼제어기법을 사용하고 있다.

• KIEE International Transactions on Power Engineering
• /
• v.5A no.3
• /
• pp.228-234
• /
• 2005

This paper presents the evaluation of reactive power pricing through the control of generator voltages under the assumption that the reactive power market has been transformed into the real power market. By applying the concept of economic dispatch, which minimizes the total cost of real power generation to reactive power generation, the algorithm for implementing reactive power pricing is proposed to determine the optimum voltage profiles of generators. It consists of reactive power voltage equation, the objective function that minimizes the total cost of reactive power generation, and linear analysis of inequality constraints in relation to the load voltages. From this algorithm, the total cost of the reactive power generation can be yielded to the minimum value within network constraints as the range of load voltages. This may provide the fair and reasonable price information for reactive power generation in the deregulated electricity market. The proposed algorithm has been tested on the IEEE 14-bus system using MATLAB.

• Journal of KIBIM
• /
• v.8 no.4
• /
• pp.23-33
• /
• 2018

Recently, the industry actively adopts the cutting-edge technologies of the fourth industrial revolution and uses them to enhance the productivity and service of mass-customization. The manufacturing industry is creating new processes and business models by achieving digital transformations through a lean start-up approach aimed at achieving the highest customer satisfaction with minimal resources. Although attempts are made to manufacture the building by introducing the latest technology in architecture, it is applied sporadically, not as an integrated system, in the entire phase of the architectural project. This paper analyzes the changes in the construction industry through the application of core technologies of the fourth industrial revolution. Design processes are analyzed for the digital transformation of the construction industry by case study of advanced architectural design practice. A novel design concept model 'Architectural lean startup' is proposed by combining the architectural process and the lean start up method. Through the design of the bus stop based on the architectural lean startup concept, it is confirmed that the designer repeats the 'Generate-Test-Analysis' to develop the design and generate the final result.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.8
• /
• pp.74-85
• /
• 2015

PCI Express is a well-known and widely used de-facto system bus standard for connecting among a processor and IO devices. PCI Express is originated from old PCI standard, and its most of applications are limited to be used within a PC or server system. But, because of its fast speed, low power consumption, and good protocol efficiency, it is considered as one of a good candidate for an alternate system interconnect for many years. In this paper, we present design, implementation and early evaluation of an alternate system interconnect by utilizing PCI Express. The developed alternate system interconnect using PCI Express (named PCIeLINK) utilizes non-transparent bridging (NTB) technic which generally used in fail-over system in PCI and PCI Express. By using NTB technic, PCI Express device can be extended to outside of a system without electrical and logical problems arising during system boot and enumeration. To build up an alternate system interconnect, we designed and implemented a network interface card having multiple PCI Express ${\times}4$ connections (theoretically 20 Gbps) and tested, The early test results revealed that an ${\times}4$ port in the card showed 8.6 Gbps peak performance for bulk transmission and 5.1 Gbps peak for normal TCP/IP transfer.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.76-84
• /
• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.3
• /
• pp.446-457
• /
• 2017

In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.

• Journal of IKEEE
• /
• v.16 no.3
• /
• pp.274-282
• /
• 2012

In this paper, we propose the design of lighting control algorithm for intelligent LED lighting system. The proposed lighting control algorithm transmitted to MCU through a data bus the environmental information detected from respectively sensor node. The MCU control software was designed to determine the level maintained to depending on the set control method by comparing the results that calculated the dimming level using a signal value. Also, it was designed to be lighting by cross-performed periodically the rotation and reverse method by created fully symmetrical pattern using the control algorithm to LED lighting device. In this paper, the proposed lighting control algorithm improved the reliability of the data sent by designed the system that can be controlled lighting to stable, and it was maintained the event delivery ratio of 91%. Also, the lighting device was decreased the luminous intensity of 32%, the power consumption of 49%, and heat generation of 32%. As a result, it were could be improved the energy efficiency that the life-cycle of LED has been increased 50%.

• Journal of KIISE:Computer Systems and Theory
• /
• v.29 no.1
• /
• pp.35-41
• /
• 2002

It is extremely important to minimize network access time in constructing a high-performance PC cluster system For an SCI based PC cluster it is possilbe to reduce the network access time by maintaining network cache in each cluster node, This paper presents a CC-NUMA card that utilizes network cache for SCI based PC clustering The CC-NUMA card is directly plugged into the PCI solot of each node, and contains shared memory network cache, and interconnection modules. The network cache is maintained for the shared memory on the PCI bus of cluster nodes. The coherency mechanism between the network cache and the shared memory is based on the IEEE SCI standard. A CC-NUMA prototype card is developed to evaluate the performance of the system. According to the experiments. the cluster system with the CC-NUMA card showed considerable improvements compared with an SCI based clustser without network cache.