• Proceedings of the Korean Society of Computer Information Conference
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• 2014.07a
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• pp.25-28
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• 2014

근래에는 대부분의 지방자치단체에서 버스정보시스템을 운영하여 버스 고객에게 다양한 정보를 제공한다. 예를 들어, 기다리는 버스의 현재 위치를 알려주는 서비스가 버스정보시스템이 제공하는 대표적인 서비스 중 하나이다. 버스정보시스템은 버스의 현재 위치를 감지하는 다양한 센서들, 센서 데이터를 수집하는 통신시스템, 수집한 데이터를 분석하여 정보를 추출하는 서버시스템 등으로 구성되며, 구축비용이 어마어마하다. 본 저자는 버스정보시스템의 구축비용을 획기적으로 절약하는 방법으로 스마트폰을 이용하는 방법을 이미 제안한 바 있다. 본 논문은 스마트폰 기반의 버스정보시스템의 서버의 구성요소 중 고객이 승차하기를 원하는 버스 노선을 알아내는 버스노선 추천 시스템을 설계한다.

• Proceedings of the KSR Conference
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• 2007.11a
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• pp.1777-1782
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• 2007

Since July in 2004, starting with urban bus reorganization of Seoul metropolitan government, the change of the public transportation which integrates the urban bus and the subway of the metropolis are being continued. But the integration of such bus and the subway is staying to only a fare system mainly, and the guidance system of the subway and the bus has not changed. So we propose the concept of the new guidance system following public transportation change tendency. At first we introduce the new information system which can guide city railroad and bus altogether, and we propose new system which can guide divided by the trunk line and the branch line instead of bus and subway. Last high-functional guidance system which can give passengers tip and hint for various and effective usage of public transportation in more complicated city transit network is introduced. This new guidance system can increase competitiveness of public transportation system and stretch transportation share of it. And that guidance system is high-class contents that all public transportation business can utilize, so it can originate new industry. In conclusion, this new innovative guidance system is important field that government, local administration and public transportation business must be concerned and develop.

• Journal of Korean Society of Transportation
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• v.20 no.1
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• pp.7-18
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• 2002

To activate public transportation service, Bucheon City built Bus Information System based on Beacon type, and operates it for no.22 line. This research analyzes an effect of BIS operations, and mainly it analyzes far reliability evaluation of bus arrival time information and passenger satisfaction about BIS. As results of reliability evaluation of arrival time information service, it is proven to be practically inappropriate to use as arrival time data because it is not only travel time between each bus stop but also previous travel time history data. In order to improve this matter, neural network model was evaluated as the most outstanding one as result of experiment in applying current arrival time Prediction model. This research cannot help limiting for evaluation of operation effect in Bucheon City because there is no Bus Information System based on GPS type in Korea. For the future ITS model city, in the case of building ITS model city based on GPS type, it is possible to compare two systems relatively. In addition to that, fur the consideration of reliability of bus arrival time information, it is required to develop Predictable model and research factors that affect to bus operation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.94-101
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• 2010

Optimization of interconnects among processors and memories becomes important as multiple processors and memories can be integrated on a Multi-Processor System-on-Chip (MPSoC). Since the optimal interconnection architecture is usually dependent on the applications, systematic design methodology for various data transfer requirements is necessary. In this paper, we focus on bus interconnection for MPSoC applications which use 4 ~ 16 processors. We propose a new systematic bus design methodology under performance constraints using Single Arbitration Multiple Bus Accesses (SAMBA) style bus architectures. Optimized bus architecture is found to satisfy performance constraints for a single or multiple applications. When compared to the unoptimized architecture, our method can reduce the bus switch logic circuits significantly (by more than 50% sometimes). Furthermore, low cost bus architectures can be found to satisfy the performance constraints for multiple applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.148-151
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• 2006

The DC power-bus' resonance is frequently attributed to EMI sources in the PCBs. Subsequently, it will ruin the digital signal integrity within one system or between adjacent systems in the form of conducted or radiated emission. Hence, since it is of importance to examine the PCB's emission, this paper sheds a light on the radiated emission from the power-bus with regards to its resonance modes. A full-wave analysis method is used to calculate the impedance and radiated electric fields and is validated by physics and an EM analysis tool.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.429-432
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• 2005

This paper investigates how the PCB power-bus structure's characteristics are influenced by the loading of decoupling capacitors that are placed close to vias, on purpose or not. It is worthwhile to see the correlated effects of the aforementioned lumped elements in that when they inevitably share one DC power-bus they will result in positive or negative changes in the PCB EMC design. The EM fields and impedance profiles are rigously calculated on the PCB power-bus cases loaded with the above components and their effects will be given to bring better PCB EMC countermeasures.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2499-2502
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• 2005

Universal Serial Bus (USB) is one of the most popular communication interfaces. When USB is used in more extended range, especially configuring home network by connecting multiple digital devices each other, USB interface uses the bandwidth in the way of Time Division Multiplexing (TDM) so that the bottleneck of bus bandwidth can be brought under the heavy traffic. In this paper, the more effective usage of bus bandwidth to overcome this situation is introduced. Basically, in order to realize the system for transferring real-time moving picture data among digital information devices, we analyze USB transfer types and descriptors and introduce the method to enhance the detailed performance of isochronous transfer that is one of USB transfer types.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.831-834
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• 1998

This paper describes a bus interface unit which is used in a 32bit high-performance multimedia RISC CPU including DSP unit. The main idea adopted in designing is that the bus interface unit enables the processor to provide on-chip functions for controlling memory and peripheral devices, including RAS-cAS multiplexing, DRAM refresh and parity generation and checking. The number of bus cycles used for a memory or I/O access is also defined by the processor, thus, no external bus controllers are required. All memories and peripheral devices can be connected directly, pin to pin, without any glue logic. That is the key point of the design.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.76-91
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• 1996

In this paper, we proposed the new medium access control protocol for the virtual token bus netowrk. The network is applied to inter-processor communication network of large capacity digital switching system and digital mobile system with distributed control architecture. in the virtual token bus netowrk, the existing medium access control protocols hav ea switchove rtime overhead when traffic load is light or asymmetric according ot arbitration address of node that has message to send. The proposed protocol optimized average message delay using cyclic bus access chain to exclude switchover time of node that do not have message to send. Therefore it enhanced bus tuilization and average message delay that degrades the performance of real time communication netowrks. It showed that the proposed protocol is more enhacned than virtual token medium access control protocol and virtual token medium access control protocol iwth reservation through performance analysis.