• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.12
• /
• pp.25-30
• /
• 2007

In this paper, we proposed a new burst-mode optical transmitter structure which is suitable for high data rate operation such as Gb/s operation. With this structure we made a 1.25Gb/s burst-mode optical transmitter including a digitally controlled APC circuit for EPON systems using commercial 0.8m BiCMOS technology. It well functioned at 1.25Gb/s and showed good eye patterns with 53.3ps jitter, 191ps rise time and 258ps fall time. To characterize the APC function we measured optical output power as increasing external voltage VREF. The optical power is linearlyproportional to VREF at the rate of 0.293mW/V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.12
• /
• pp.31-38
• /
• 2003

In this paper, we proposed a new structural AGC(Automatic Gain Control) circuit with extremely short settling time using high speed operation characteristics of a clipper. We investigated its operation characteristics in analysis. We also designed a burst-mode preamplifier for 1.25Gbps EPON systems using commercial foundry and investigated its characteristics by comparing the results of the designed and those of the analyzed. The characteristics of the designed circuit are in good agreement with those of the analyzed. As a result, it is shown that it is possible to realize extremely short settling time of under 1㎱.

• Journal of Advanced Navigation Technology
• /
• v.13 no.3
• /
• pp.337-343
• /
• 2009

In this paper, we proposed a burst mode symbol timing recovery unit that is applicable to the VDL Mode-2 using D8PSK modulation. A method that IIR loop filter is used to minimize symbol timing error is hard to apply to burst mode because its convergence time is long. That is, the fast convergence property is important. In this paper, the proposed method takes one sample which has maximum symbol power after the initial synchronization has been achieved by using preambles. The main principle of operation is that the unit moves one sample clock to advance or retard according to symbol power. We verify that the proposed method is operated well in ${\pm}100$ ppm or greater through the test results between Australia ADS Corp. transmitter and the designed receiver.

• Proceedings of the IEEK Conference
• /
• 2000.11a
• /
• pp.109-112
• /
• 2000

The satellite communications are expected to play an important role to provide broadband multimedia services in the 21st century. According to this requirements, this paper describes the design and implementation of ATM-based high speed satellite modem ASIC chipset. The ASIC chip consists of three main parts, CODEC, Modulator and Demodulator. It supports burst and continuous mode operation with TDMA frame consisted of Reference bursts, Inbound burst, and Traffic burst. The maximum transmission rate is OC-3 (155Mbps) and the maximum operating clock speed is 220MHz. This ASIC chip was implemented with 0.25um CMOS technology.

• The Magazine of the IEIE
• /
• v.30 no.3
• /
• pp.287-287
• /
• 2003

• The Magazine of the IEIE
• /
• v.30 no.3
• /
• pp.73-80
• /
• 2003

• The Transactions of the Korean Institute of Power Electronics
• /
• v.14 no.4
• /
• pp.299-306
• /
• 2009

Recently, although the power consumption of the flyback converter at the light load and standby power load was minimized by the burst mode operation of PWM IC, flyback converter has still the low efficiency characteristics by the high magnetizing current flowing through magnetizing inductance of transformer. This paper proposes a novel flyback converter with an improved efficiency characteristics and the reduced magnetizing current at the light load and standby power load. Prototype of the 70W multi-output flyback converter for an auxiliary power module of 50 inch PDP TV is built and the experimental results are described.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.16 no.1
• /
• pp.88-95
• /
• 2011

In this paper, a new standby-mode control method for multiple output switching-mode power-supply is suggested, which uses the control signal of the feedback compensator of the inner loop in the linear voltage regulator located at the transformer secondary side, as the load current information. Conventional method has a problem that standby mode occurs depending only on the load condition of the main controller output, which makes the other secondary side output very inaccurate by burst mode operation. The proposed method detects all the load current information and operates in burst mode only when the all of them are light load condition. Minimum of the additional components are required for the implementation of the proposed method because the load information is obtained from the existing feedback circuit of the post-stage linear regulator. In this paper, the operating principles of the proposed standby-mode circuit are presented with an numerical analysis, and are verified by 25W hardware prototype implementation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.4
• /
• pp.984-995
• /
• 1996

Data errors according to the various noises caused in the satellite communication links are corrected by the Viterbi decoding algorithm which has extreme error correcting capability. In this paper, we designed and implemented a convolutional encoder and Viterbi decoder ASIC which is used to encode the input data at the transmit side and correct the errors of the received data at the receive side for use in the VSAT communication system. And this chip may be used in any BPSK, QPSK, or OQPSK transmission system. The ambiguity resolver corrects PSK modem ambiguities by delaying, interting, and/or exchanging code symbol to restore their original sequence and polarity. In case of previous decoding system, ambiguity state(AS) of data is resolved by external control logic and extra redundancy data are needed to resolve AS. But, by adopting decoder proposed in this paper, As of data is resolved automatically by internal logic of decoder in case of continuous mode, and by external As line withoug extra redudancy data in burst mode case. So, decoding parts are simple in continuous mode and transmission efficiency is increased in bust mode. The features of this chip are full duplex operation with independent transmit and receive control and clocks, start/stop inputs for use in burst mode systems, loopback function to verify encoder and decoder, and internal or external control to resolve ambinguity state. For verification of the function and performance of a fabricated ASIC chip, we equiped this chip in the Central and Remote Earth Station of VSAT system, and did the performance test using the commerical INTELSAT VII under the real satellite link environmens. The results of test were demonstrated the superiority of performance.

• International Journal of Naval Architecture and Ocean Engineering
• /
• v.7 no.3
• /
• pp.435-451
• /
• 2015

Evaluation of the performance of aging structures is essential in the oil and gas industry, where the inaccurate prediction of structural performance can have significantly hazardous consequences. The effects of structure failure due to the significant reduction in wall thickness, which determines the burst strength, make it very complicated for pipeline operators to maintain pipeline serviceability. In other words, the serviceability of gas pipelines and elbows needs to be predicted and assessed to ensure that the burst or collapse strength capacities of the structures remain less than the maximum allowable operation pressure. In this study, several positions of the corrosion in a subsea elbow made of API X42 steel were evaluated using both design formulas and numerical analysis. The most hazardous corrosion position of the aging elbow was then determined to assess its serviceability. The results of this study are applicable to the operational and elbow serviceability needs of subsea pipelines and can help predict more accurate replacement or repair times.