• Title/Summary/Keyword: Bump design

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Study of a Low-Temperature Bonding Process for a Next-Generation Flexible Display Module Using Transverse Ultrasound (횡 초음파를 이용한 차세대 플렉시블 디스플레이 모듈 저온 접합 공정 연구)

  • Ji, Myeong-Gu;Song, Chun-Sam;Kim, Joo-Hyun;Kim, Jong-Hyeong
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.36 no.4
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    • pp.395-403
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    • 2012
  • This is direct bonding many of the metal bumps between FPCB and HPCB substrate. By using an ultrasonic horn mounted on an ultrasonic bonding machine, it is possible to bond gold pads onto the FPCB and HPCB at room temperature without an adhesive like ACA or NCA and high heat and solder. This ultrasonic bonding technology minimizes damage to the material. The process conditions evaluated for obtaining a greater bonding strength than 0.6 kgf, which is commercially required, were 40 kHz of frequency; 0.6MPa of bonding pressure; and 0.5, 1.0, 1.5, and 2.0 s of bonding time. The peel off test was performed for evaluating bonding strength, which was found to be more than 0.80 kgf.

Design of a Silicon Neuron Circuit using a 0.18 ㎛ CMOS Process (0.18 ㎛ CMOS 공정을 이용한 실리콘 뉴런 회로 설계)

  • Han, Ye-Ji;Ji, Sung-Hyun;Yang, Hee-Sung;Lee, Soo-Hyun;Song, Han-Jung
    • Journal of the Korean Institute of Intelligent Systems
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    • v.24 no.5
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    • pp.457-461
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    • 2014
  • Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.

Optimization of Power Bumps and TSVs with Optimized Power Mesh Structure for Power Delivery Network in 3D-ICs (3D-IC 전력 공급 네트워크를 위한 최적의 전력 메시 구조를 사용한 전력 범프와 TSV 최소화)

  • Ahn, Byung-Gyu;Kim, Jae-Hwan;Jang, Cheol-Jon;Chong, Jong-Wha
    • Journal of IKEEE
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    • v.16 no.2
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    • pp.102-108
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    • 2012
  • 3-dimensional integrated circuits (3D-ICs) have some problems for power delivery network design due to larger supply currents and larger power delivery paths compared to 2D-IC. The power delivery network consists of power bumps & through-silicon-vias (TSVs), and IR-drop at each node varies with the number and location of power bumps & TSVs. It is important to optimize the power bumps & TSVs while IR-drop constraint is satisfied in order to operate chip ordinarily. In this paper, the power bumps & TSVs optimization with optimized power mesh structure for power delivery network in 3D-ICs is proposed.

Simulation Study of a Large Area CMOS Image Sensor for X-ray DR Detector with Separate ROICs (센서-회로 분리형 엑스선 DR 검출기를 위한 대면적 CMOS 영상센서 모사 연구)

  • Kim, Myung Soo;Kim, Hyoungtak;Kang, Dong-uk;Yoo, Hyun Jun;Cho, Minsik;Lee, Dae Hee;Bae, Jun Hyung;Kim, Jongyul;Kim, Hyunduk;Cho, Gyuseong
    • Journal of Radiation Industry
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    • v.6 no.1
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    • pp.31-40
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    • 2012
  • There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.

Analysis of BWIM Signal Variation Due to Different Vehicle Travelling Conditions Using Field Measurement and Numerical Analysis (수치해석 및 현장계측을 통한 차량주행조건에 따른 BWIM 신호 변화 분석)

  • Lee, Jung-Whee
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.24 no.1
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    • pp.79-85
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    • 2011
  • Bridge Weigh-in-Motion(BWIM) system calculates a travelling vehicle's weight without interruption of traffic flow by analyzing the signals that are acquired from various sensors installed in the bridge. BWIM system or data accumulated from the BWIM system can be utilized to development of updated live load model for highway bridge design, fatigue load model for estimation of remaining life of bridges, etc. Field test with moving trucks including various load cases should be performed to guarantee successful development of precise BWIM system. In this paper, a numerical simulation technique is adopted as an alternative or supplement to the vehicle traveling test that is indispensible but expensive in time and budget. The constructed numerical model is validated by comparison experimentally measured signal with numerically generated signal. Also vehicles with various dynamic characteristics and travelling conditions are considered in numerical simulation to investigate the variation of bridge responses. Considered parameters in the numerical study are vehicle velocity, natural frequency of the vehicle, height of entry bump, and lateral position of the vehicle. By analyzing the results, it is revealed that the lateral position and natural frequency of the vehicle should be considered to increase precision of developing BWIM system. Since generation of vehicle travelling signal by the numerical simulation technique costs much less than field test, a large number of test parameters can effectively be considered to validate the developed BWIM algorithm. Also, when artificial neural network technique is applied, voluminous data set required for training and testing of the neural network can be prepared by numerical generation. Consequently, proposed numerical simulation technique may contribute to improve precision and performance of BWIM systems.

A Design of Digital CMOS X-ray Image Sensor with $32{\times}32$ Pixel Array Using Photon Counting Type (포톤 계수 방식의 $32{\times}32$ 픽셀 어레이를 갖는 디지털 CMOS X-ray 이미지 센서 설계)

  • Sung, Kwan-Young;Kim, Tae-Ho;Hwang, Yoon-Geum;Jeon, Sung-Chae;Jin, Seung-Oh;Huh, Young;Ha, Pan-Bong;Park, Mu-Hun;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.7
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    • pp.1235-1242
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    • 2008
  • In this paper, x-ray image sensor of photon counting type having a $32{\times}32$ pixel array is designed with $0.18{\mu}m$ triple-well CMOS process. Each pixel of the designed image sensor has an area of loot $100{\times}100\;{\mu}m2$ and is composed of about 400 transistors. It has an open pad of an area of $50{\times}50{\mu}m2$ of CSA(charge Sensitive Amplifier) with x-ray detector through a bump bonding. To reduce layout size, self-biased folded cascode CMOS OP amp is used instead of folded cascode OP amp with voltage bias circuit at each single-pixel CSA, and 15-bit LFSR(Linear Feedback Shift Register) counter clock generator is proposed to remove short pulse which occurs from the clock before and after it enters the counting mode. And it is designed that sensor data can be read out of the sensor column by column using a column address decoder to reduce the maximum current of the CMOS x-ray image sensor in the readout mode.

OPERATIONAL MODEL OF TIME-KEEPING SYSTEMS OF HEUMGYEONGGAK-NU (흠경각루 시보시스템의 작동모델)

  • KIM, SANG HYUK;YUN, YONG-HYUN;MIHN, BYEONG-HEE;LEEM, BYONG GUEN;YOON, MYUNG KYOON;LEEM, BYONG SI
    • Publications of The Korean Astronomical Society
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    • v.34 no.3
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    • pp.31-40
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    • 2019
  • We study the internal structure under the artificial mountain of Heumkyeonggak-nu, a Korean water-powered clock in the early Joseon dynasty. All the puppets on the artificial mountain are driven by the rotational force generated by the water wheel at their designated time. We design a model that work with three parts of the artificial mountain. At the upper part of the artificial mountain to the east, west, north and south, there are four puppets called the Four Mystical Animal Divinity and four ladies called the Jade Lady respectively. The former rotates a quarter every double hour and the latter rings the bell every hour. In the middle part of this mountain is the timekeeping platform with four puppets; the Timekeeping Official (Hour Jack), the Bell-, Drum-, and Gong-Warriors. The Hour Jack controls time with three warriors each hitting his own bell, drum, and gong, respectively. In the plain there are 12 Jade Lady puppets (the lower ladies) combined with 12 Oriental Animal Deity puppets. In his own time a lady doll pops out of the hole and her animal doll gets up. Two hours later, the animal deity lies down and his lady hides in the artificial plain. These puppets are regularly moved by the signal such as iron balls, bumps, levers, and so on. We can use balls and bumps to explain the concept of the Jujeon system. Iron balls were used to manipulate puppets of the timekeeping mechanism in Borugak-nu, another Korean water-powered clock in Joseon dynasty, which was developed earlier than Heumgyeonggak-nu. According to the North Korea's previous study (Choi, 1974), it is obvious that bumps were used in the internal structure of Heumgyeonggak-nu. In 1669, The armillary clock made by Song, I-young was also utilized bumps. Finally we presented mock-ups of three timekeeping systems.