• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.180-183
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• 2006

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

• Journal of the Korean Ceramic Society
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• v.49 no.6
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• pp.637-641
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• 2012

Due to its high production cost and relatively high energy consumption during the Siemens process, poly-silicon makers have been continuously and eagerly sought another silicon route for decades. One candidate that consumes less energy and has a simpler acidic and metallurgical purification procedure is upgraded metallurgical-grade (UMG) silicon. Owing to its low purity, UMG silicon often requires special steps to minimize the impurity effects and to remove or segregate the metal atoms in the bulk and to remove interfacial defects such as precipitates and grain boundaries. A process often called the 'gettering process' is used with phosphorus diffusion in this experiment in an effort to improve the performance of silicon solar cells using UMG silicon. The phosphorous gettering processes were optimized and compared to the standard POCl process so as to increase the minority carrier lifetime(MCLT) with the duration time and temperature as variables. In order to analyze the metal impurity concentration and distribution, secondary ion mass spectroscopy (SIMS) was utilized before and after the phosphorous gettering process.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.4
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• pp.26-32
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• 1978

For a long life photovoltaic cell the degradation of the device characteristics with 1 MeV electron radiation must be known so as to be able to predict the life of the cell. Hence, a study was made of radiation damage effects on the bulk properties of the silicon crystal. From the results of the data, it is concluded that there appeared to be a steads rotate damage level reached in f type material.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.470-480
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• 2016

The reversal of a silicon chip to find out its security structure is common and possible at the present time. Thanks to reversing, it is possible to use a probing attack to obtain useful information such as personal information or a cryptographic key. For this reason, security-related blocks such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and RSA (Rivest Shamir Adleman) engines should be located in the lower layer of the chip to guard against a probing attack; in this regard, the addition of a silicon-surface-protection layer onto the chip surface is a crucial protective measure. But, for manufacturers, the implementation of an additional silicon layer is burdensome, because the addition of just one layer to a chip significantly increases the overall production cost; furthermore, the chip size is increased due to the bulk of the secure logic part and routing area of the silicon protection layer. To resolve this issue, this paper proposes a practical silicon-surface-protection method using a metal layer that increases the security level of the chip while minimizing its size and cost. The proposed method uses a shift register for the alternation and variation of the metal-layer data, and the inter-connection area is removed to minimize the size and cost of the chip in a more extensive manner than related methods.

• Interaction and multiscale mechanics
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• v.1 no.2
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• pp.303-315
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• 2008

In this paper, thermodynamical properties of crystalline silicon under strain are calculated using classical molecular dynamics (MD) simulations based on the Tersoff interatomic potential. The Helmholtz free energy of the silicon crystal under strain is calculated by using the ensemble method developed by Frenkel and Ladd (1984). To account for quantum corrections under strain in the classical MD simulations, we propose an approach where the quantum corrections to the internal energy and the Helmholtz free energy are obtained by using the corresponding energy deviation between the classical and quantum harmonic oscillators. We calculate the variation of thermodynamic properties with temperature and strain and compare them with results obtained by using the quasi-harmonic model in the reciprocal space.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.162-165
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• 1991

Oxygen behaviors in CZ-silicon wafer, grown by the Lucky Advanced Materials Inc. that is a pioneer of silicon material industries in Korea, were investigated to simulate effects on the device performance of oxygen, neglecting the effect of other impurity content, defects and thermal history. Silicon wafers were annealed through simulated 16K SRAM thermal cycle. As initial oxygen concentration increased up to 16.7ppma the amount of oxygen precipitation increased up to 10.6ppma and the bulk microdefect density increased up to $10.3{\times}10^3/mm^2$, but the depth of the denuded zone decreased to $5.0{\mu}m$

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1054-1056
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• 2002

High temperature Kermal diffusion from $POCl_3$ source usually used for conventional process through put of a cell manufacturing line and potentially reduce cell efficiency through bulk like time degradation. To fabricate high efficiency solar cells with minimal thermal processing, spin-on-doping(SOD) technique can be employed to emitter diffusion of a silicon solar cell. A technique is presented to emitter doping of a mono-crystalline solar cell using spin-on doping (SOD). Moreover it is shown that the sheet resistance variation with RTA temperature and time fer mono-crystalline and multi-crystalline silicon samples. This novel SOD technique was successfully used to produces 11.3% efficiency l04mm by 104mm size mono-crystalline silicon solar cells.

• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.1-11
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• 2018

Several industrial applications such as space exploration, aerospace, automotive, the downhole oil and gas industry, and geothermal power plants require specific electronic systems under extremely high temperatures. For the majority of such applications, silicon-based technologies (bulk silicon, silicon-on-insulator) are limited by their maximum operating temperature. Silicon carbide (SiC) has been recognized as one of the prime candidates for providing the desired semiconductor in extremely high-temperature applications. In addition, it has become particularly interesting owing to a Si-compatible process technology for dedicated devices and integrated circuits. This paper briefly introduces a variety of SiC-based integrated circuits for use under extremely high temperatures and covers the technology trend of SiC CMOS devices and processes including the useful implementation of SiC ICs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.3
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• pp.89-95
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• 2001

The CZ-silicon crystal was annealed at $1350^{\circ}C$ to dissolve the vacancy type grown-in defects. A this temperature, the equilibrium concentration of the oxygen in the silicon crystal is around $1.7{\times}10^{18}$ which induces the oxygen undersaturation in the silicon crystal. This situation results in the faster dissolution of the grown-in defects in the bulk of the silicon wafer than near the surface. This indicates the possibility that the presence of the higher concentration of silicon interstitial hinders the dissolution of the grown-in defects, which were known to compose of the vacancy clusters with surrounding silicon oxide film. This expectation was confirmed by the observation that the slower dissolution of the grown-in defects near the surface of the silicon wafer in the oxygen atmosphere than in the argon atmosphere. This result is quite opposite to the previous argument hat presence of the excess silicon interstitial leads to faster dissolution of the vacancy type defects.