• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.64.2-64.2
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• 2011

a-Si 박막 태양전지는 a-Si:H을 유리 기판 사이에 주입해 만드는 태양전지로, 뛰어난 적용성과 경제성을 지녔으나 c-Si 태양전지에 비해 낮은 변환 효율을 보이는 단점이 있다. 변환 효율을 높이기 위한 연구 방법으로는 a-Si 박막 태양전지 단일cell 제작 시 high Bandgap을 가지는 p-layer를 사용함으로 높은 Voc와 Jsc의 향상에 기여할 수 있는데, 이 때 p-layer의 defect 증가와 activation energy 증가도 동시에 일어나 변환 효율의 증가폭을 감소시킨다. 이를 보완하기 위해 본 실험에서는 p-layer에 기존의 p-a-Si:H를 사용함과 동시에 high Bandgap의 buffer layer를 p-layer와 i-layer 사이에 삽입함으로써 그 장점을 유지하고 높은 defect과 낮은 activation energy의 영향을 최소화하였다. ASA 시뮬레이션을 통해 a-Si:H보다 high Bandgap을 가지는 a-SiOx 박막을 사용하여 p-type buffer layer의 두께를 2nm, Bandgap 2.0eV, activation energy를 0.55eV로 설정하고, i-type buffer layer의 두께를 2nm, Bandgap 1.8eV로 설정하여 삽입하였을 때 박막 태양전지의 변환 효율 10.74%를 달성할 수 있었다. (Voc=904mV, Jsc=$17.48mA/cm^2$, FF=67.97).

• Korean Journal of Materials Research
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• v.24 no.12
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• pp.645-651
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• 2014

GaN is most commonly used to make LED elements. But, due to differences of the thermal expansion coefficient and lattice mismatch with sapphire, dislocations have occurred at about $109{\sim}1010/cm^2$. Generally, a low temperature GaN buffer layer is used between the GaN layer and the sapphire substrate in order to reduce the dislocation density and improve the characteristics of the thin film, and thus to increase the efficiency of the LED. Further, patterned sapphire substrate (PSS) are applied to improve the light extraction efficiency. In this experiment, using an AlN buffer layer on PSS in place of the GaN buffer layer that is used mainly to improve the properties of the GaN film, light extraction efficiency and overall properties of the thin film are improved at the same time. The AlN buffer layer was deposited by using a sputter and the AlN buffer layer thickness was determined to be 25 nm through XRD analysis after growing the GaN film at $1070^{\circ}C$ on the AlN buffer CPSS (C-plane Patterned Sapphire Substrate, AlN buffer 25 nm, 100 nm, 200 nm, 300 nm). The GaN film layer formed by applying a 2 step epitaxial lateral overgrowth (ELOG) process, and by changing temperatures ($1020{\sim}1070^{\circ}C$) and pressures (85~300 Torr). To confirm the surface morphology, we used SEM, AFM, and optical microscopy. To analyze the properties (dislocation density and crystallinity) of a thin film, we used HR-XRD and Cathodoluminescence.

• Journal of the Korean Magnetics Society
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• v.12 no.4
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• pp.132-136
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• 2002

Enhancement of crystallinity and exchange bias characteristics for NiFe/FeMn/NiFe trilayer with Si buffer layer fabricated by ion-beam deposition were examined. A Si buffer layer promoted (111) texture of fcc crystallities in the initial growth region of NiFe layer deposited on it. FeMn layers deposited on Si/NiFe bilayer exhibited excellent (111) crystal texture. The antiferromagnetic FeMn layer between top and bottom NiFe films with the buffer Si 50 ${\AA}$-thick induced a large exchange coupling field Hex with a different dependence. It was found that H$\sub$ex/ of the bottom and top NiFe films with Si buffer layer revealed large value of about 110 Oe and 300 Oe, respectively. In the comparison of two Ta and Si buffer layers, the NiFe/FeMn/NiFe trilayer with Si could possess larger exchange coupling field and higher crystallinity.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.5
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• pp.9-16
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• 2004

The data link layer of the PCI Express must have the transmitting buffer that contains the packets to transmit next time. Also it must have the retry buffer that contains the packets which were already transmitted but have not been acknowledged by the corresponding target device. In the separated buffer architecture, the data link layer can not transmit the packets in the transmitting buffer if the reiry buffer space is not enough. In this paper, we propose an efficient buffer architecture which merges the transmitting buffer and the retry buffer to a single buffer. Since the proposed buffer can dynamically assign the size of the transmitting buffer and the retry buffer, it can improve the buffer usage efficiency and the data transfer efficiency. The simulation result shows that the proposed buffer has the higher data transfer efficiency than the separated buffer architecture about 39% when the total buffer size is 8K byte.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.23-26
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• 2003

The BLT thin film and MgO buffer layer were fabricated using a metalorganic decomposition method and the DC sputtering technique. The MgO thin film was deposited as a buffer layer on $SiO_2/Si$ and BLT thin films were used as a ferroelectric layer. The electrical of the MFIS structure were investigated by varying the MgO layer thickness. TEM showsno interdiffusion and reaction that suppressed by using the MgO film as abuffer layer. The width of the memory window in the C-Y curves for the MFIS structure decreased with increasing thickness of the MgO layer Leakage current density decreased by about three orders of magnitude after using MgO buffer layer. The results show that the BLT and MgO-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.04a
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• pp.140-142
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• 2003

ZnO thin films are demanded for device applications, so ZnO buffer layer was used to improve for good properties of ZnO thin film. In this study, the structural, electrical and optical properties of ZnO thin films deposited with various buffer thickness was investigated by X-ray diffraction (XRD), Hall measurements, Photoluminescence(PL). ZnO buffer layer and ZnO thin films on sapphire($Al_{2}O_{3}$) substrate have been deposited $200^{\circ}C$ and $400^{\circ}C$ respectively by pulsed laser deposition. It is observed the variety of lattice constant of ZnO thin film by (101) peak position shift with various buffer thickness. It is founded that ZnO thin film with buffer thickness of 20 nm was larger resistivity of 200 factor and UV/visible of 2.5 factor than that of ZnO thin films without buffer layer. ZnO thin films with buffer thickness of 20 nm have shown the most properties.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.224-227
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• 2001

ZnO buffer layers were used to grow ZnO films on c-plane sapphire substrates. The role of ZnO buffer layers in the growth of ZnO thin films on sapphire substrates was investigated by scanning electron microscopy, X-ray diffraction, and Photolumminescence(PL) measurements. At the optimized ZnO buffer layer thickness of 100 $\AA$, FWHM of $\theta$ -rocking curve of ZnO thin films was minimized to 0.73 degrees and room temperature PL spectra showed that deep level emission was not hardly seen. The optimization of the ZnO buffer layer thickness resulted in improvements of the surface morphology and crystalline quality of ZnO thin films.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.269-271
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• 2004

In this report, high-performance organic light-emitting diodes (OLEDs) with polytetrafluoroethylene (Teflon) buffer layer are demonstrated. Compared with conventional buffer layer, copper phthalocaynine (CuPc), Teflon film shows lower absorption in the wavelength from 200nm to 800nm The OLEDs with Teflon and CuPc buffer layer were fabricated under same conditions, and the device performances were compared. The results indicate that when the thickness of Teflon is 1.5nm, the performance of OLEDs is greatly enhanced with an efficiency of 9.0cd/A at the current density of 100mA/$cm^2$, while the device with an optimized 30-nm-thick CuPc buffer layer only shows an efficiency of6.4cd/A at the same current density.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.240-242
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• 1993

A novel structure, which can suppress latch-up phenomena, is proposed and verified by the PISCESIIB simulation. It is shown that this structure employing the selective N+ buffer layer increases latch-up current density due to suppression of the current flowing through the p-body. The width of the N+ buffer layer is optimized considering the trade-off between the latch-up current density and the forward voltage drop. The selective buffer layer results in an improved trade-off relationship compared with the uniform buffer layer.

• Transactions on Electrical and Electronic Materials
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• v.12 no.3
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• pp.102-105
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• 2011

This work describes the characteristics of zinc oxide (ZnO) thin films formed on a polycrystalline (poly) 3C-SiC buffer layer using a sol-gel process. The deposited ZnO films were characterized using X-ray diffraction, scanning electron microscopy, and photoluminescence (PL) spectra. ZnO thin films grown on the poly 3C-SiC buffer layer had a nanoparticle structure and porous film. The effects of post-annealing on ZnO film were also studied. The PL spectra at room temperature confirmed the crystal quality and optical properties of ZnO thin films formed on the 3C-SiC buffer layer were improved due to close lattice mismatch in the ZnO/3C-SiC interface.