• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12B
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• pp.2320-2334
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• 1999

In this paper, we propose multiple IS-MMBS service schemes for very low power and micro-size RMIMS (radio-interfaced micro information monitoring system) terminals. In MMBS service area, when new arrival RMIMS terminals have real-time traffic characteristic or large traffic bandwidth, only single IS-MMBS service scheme can not guarantee RMIMS terminal's QoS(quality of service) such as buffer overflow or packet loss. In this case, the proposed multiple IS-MMBS service schemes can be effectively used for QoS service of RMIMS terminal. According to clustering method of RMIMS terminals and MMBS segment method, the proposed schemes can be divided into terminal segment method, region segment method, application based segment method, traffic type based segment method, overlapping segment method and hybrid segment method

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.236-247
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• 2002

We propose a cell－multiplexing scheme for the real－time communication service in ATM network and a new service discipline guarantee end-to-end delay based on pseudo-isochronous cell switching. The proposed scheme consists of two level frame hierarchy, upper and lower frame, which is used to assign the bandwidth and to guarantee the requested delay bound, respectively. Since the Proposed algorithm employs two level frame hierarchy, it can overcome the coupling problem which is inherent to the framing strategy It can be comparatively reduce the complexity, and still guarantee the diverse delay bounds of end-to-end. Besides, it consists of two components, traffic controller and scheduller, as the imput traffic description model and regulates the input traffic specification. The function of the traffic controller is to shape real -time traffic to have the same input pattern at every switch along the path. The end-to-end delay is bounded by the scheduller which can limit the delay variation without using per-session jitter controllers, and therefore it can decrease the required buffer size. The proposed algorithm can support the QoS's of non-real time traffic as well as those of real time traffic.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1734-1740
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• 2012

In this paper, we propose a FSOURCE circuit which requires such a small switching current that an eFuse OTP memory can be programmed in the post-package state of the PMIC chips using a single power supply. The proposed FSOURCE circuit removes its short-circuit current by using a non-overlapped clock and reduces its maximum current by reducing the turned-on slope of its driving transistor. Also, we propose a DOUT buffer circuit initializing the output data of the eFuse OTP memory with arbitrary data during the power-on reset mode. We design a 24-bit differential paired eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.445-453
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• 2002

We propose a cell-multiplexing scheme for the real-time communication service in ATM network and a new service discipline guarantee end-to-end delay based on pseudo-isochronous cell switching. The proposed scheme consists of two level frame hierarchy, upper and lower frame, which is used to assign the bandwidth and to guarantee the requested delay bound, respectively. Since the proposed algorithm employs two level frame hierarchy, it can overcome the coupling problem which is inherent to the framing strategy. The proposed scheme consists of two components, traffic controller and scheduller, as the imput traffic description model and regulates the input traffic specification. The function of the traffic controller is to shape real-time traffic to have the same input pattern at every switch along the path. The end-to-end delay is bounded by the scheduller which can limit the delay variation without using per-session jitter controllers, and therefore it can decrease the required buffer size. The proposed algorithm can support the QoS's of non-real time traffic as well as those of real time traffic

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.5C
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• pp.534-539
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• 2006

In this paper, we propose a new frame prediction filtering technique and a hardware(H/W) architecture for scalable video coding. We try to evaluate MCTF(motion compensated temporal filtering) and hierarchical B-picture which are a technique for eliminate correlation between video frames. Since the techniques correspond to non-causal system in time, these have fundamental defects which are long latency time and large size of frame buffer. We propose a new architecture to be efficiently implemented by reconfiguring non-causal system to causal system. We use the property of a repetitive arithmetic and propose a new frame prediction filtering cell(FPFC). By expanding FPFC we reconfigure the whole arithmetic architecture. After the operational sequence of arithmetic is analyzed in detail and the causality is imposed to implement in hardware, the unit cell is optimized. A new FPFC kernel was organized as simple as possible by repeatedly arranging the unit cells and a FPFC processor is realized for scalable video coding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.6-13
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• 2011

Due to its robustness to illumination change, normalized cross-correlation based similarity measurement is widely used in many machine vision applications. However, its inefficient computation structure is not adequate for real-time embedded vision system. In this paper, we present an efficient hardware architecture based on a normalized cross correlation (NCC) for fast image similarity measure. The proposed architecture simplifies window-sum process of the NCC using the integral-image. Relieving the overhead to constructing integral image, we make it possible to process integral image construction at the same time that pixel sequences are inputted. Also the proposed segmented integral image method can reduce the buffer size for storing integral image data.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.124-131
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• 2014

This paper describes a design of an adaptive baseband modem based on TDMA(time division multiple access) with a relay protocol function for wireless personal area networks. The designed baseband modem is controlled by a master synchronization signal and can be configured a relay network up to 14 hops. For efficient data relay communications, the internal buffer design is optimized by implementing a priority memory bus controller to a single port memory. And the priority memory bus controller is also designed to minimize the number of synthesized logic gates. To implement the synchronization function of the narrowband TDMA relay communication, the number of gates has been reduced by dividing the frame synchronization circuits and the network slot synchronization circuits. By using these methods, the number of gates are used about 37%(34,000 gates) on Xilinx FPGA XC6SLX9 which has 90,000 gates. For the 1024-bit frame size with a 32-bit synchronization word, the communication reception rate is 96.4%. The measured maximum transmission delay of the designed baseband modem is 230.4 msec for the 14-hop relay communication.

• Journal of Environmental Science International
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• v.23 no.7
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• pp.1349-1358
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• 2014

This study suggests plan of green space management based on the result of research apprehending the characteristic through sorting types of city thermal environment targeting summer which thermal pollution is the most serious. Considering anthropogenic heat, development level of wind road, thermal environment, as a result of types of thermal environment process, it is appeared 36 types, and 10 types is relevant of this research subject. Type I-1, size of building is large, artificial covering area is wide, and thermal load of anthropogenic heat is high, type II-1, development condition of wind road is incomplete as IIlevel, entering cold air is difficult and thermal management and improvement is needed area. Type III-1, scale is large and it is area of origin of cold air, development level of wind road is mostly favorable, type III-2 is revealed as smaller scale than III-1, and small area of origin of cold air. Type IV, anthropogenic heat is $81{\sim}150W/m^2$, average, but development function of wind road is very favorable. Type V, large area of thermal load and the origin of cold air are distributed as similar ratio, and level of development function of wind road is revealed as II level. According to standard of type classification of thermal environment, as a result of suggesting plan of green space management and biotops area ratio, type I-1 is buffer green space and waterway creation, goal biotops area ratio 35%, type II-1 afforestation in site and goal biotops area ratio 40%, type III-1, preservation plan to display the current function continuously is requested. Type IV suggests afforestation of stream current, and type V suggests quantitative increase of green space and goal biotops area ratio 45%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.65-73
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• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.722-737
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• 2011

In this paper, we propose an estimation of network jitter that occurs when transmitting TCP packets containing MPEG-2 TS in progressive streaming service over wired or wireless Internet networks. Based on the estimated network jitter size, we can calculate required de-jitter buffering time to absorb the network jitter at the receiver side. For this purpose, by exploiting the PCR timestamp existing in the TS packet header, we create a new timestamp information that is marked in the optional field of TCP packet header to estimate the network jitter. By using the proposed de-jitter buffering scheme, it is possible to employ the conventional T-STD buffer model without any modification in the progressive streaming service over IP networks. The proposed method can be applicable to the recently developed international standard, MPEG DASH (dynamic adaptive streaming over HTTP) technology.