• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.134-141
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• 2022

This study presents a method for reducing current distortion that occurs when a dual-buck inverter generates reactive power. Dual-buck inverters, which are only capable of unity power factor operation, can generate reactive power capabilities by modifying a modulation technique. However, under non-unity power factor conditions, current distortion occurs at zero-crossing points of grid voltage and output current. This distortion is caused by parasitic capacitors, dead-time, and discontinuous conduction mode operation. This study proposes a modified modulation method to alleviate the current distortion at zero-crossing point of the grid voltage. A repetitive controller is applied to reduce this distortion of the output current. A 1 kVA prototype is built and tested. Simulation and experimental results demonstrate the effectiveness of the proposed method.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.160-162
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• 2020

A control technique for the auxiliary buck/boost converter is proposed herein to improve the load transient response of the buck converter. The proposed technique improves the system efficiency by enabling the soft switching operation of the auxiliary converter. The design guidelines for achieving capacitor charge balance for the output capacitor during the transient are also presented herein. The experimental results revealed that the output voltage undershoot and settling time during the load step-up transient were 40 mV and 14 ㎲, respectively, and the output voltage overshoot and settling time during the load step-down transient were 35 mV and 21 ㎲, respectively. The performance and effectiveness of the proposed technique were experimentally verified using a prototype buck converter with a 15-V input, 3.3-V output, and 200-kHz switching frequency.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.371-378
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• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.24-31
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• 2008

Power converters are becoming an essential block in modem mobile multimedia application. This paper presents a high performance DC-DC buck converter for mobile applications. Controller of DC-DC buck converter is designed by current-mode control method. An current-mode DC-DC converter is implemented in a standard $0.18{\mu}m$ CMOS process, and the overall die size was $1.2mm^2$. The peak efficiency was 86 % with a switching frequency of $1\sim1.5MHz$ and a maximum load current of 400mA.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.394-399
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• 2007

In this paper, we study on a novel Buck-Boost converter of high efficiency by soft switching method. The proposed Buck-Boost converter is applied to new soft switching method in restraint of increment of switching power loss in the conventional Buck-Boost converter. The soft switching circuit is designed to modification of a energy storage inductor and a snubber circuit used by the conventional converter, and then the proposed converter is simplified. The controlling switches of the proposed converter is operated with soft switching by a partial resonance behavior. The output voltage of the converter is regulated by PWM control technique. The discontinuous mode action of current flowing into inductor makes to simplify control method and control components. The proposed Buck-Boost converter is compared with the conventional converter. Some computer simulative results and experimental results are confirmed to the validity of the analytical results.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1298-1307
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• 2017

The constant on-time current-mode controlled (COT-CMC) switching dc-dc converter is stable, with no subharmonic oscillation in its current loop when a voltage ripple in its outer voltage loop is ignored. However, when its output capacitance is small or its feedback gain is high, subharmonic oscillation may occur in a COT-CMC buck converter with a proportional-integral (PI) compensator. To investigate the subharmonic instability of COT-CMC buck converters with a PI compensator, an accurate reduced-order asynchronous-switching map model of a COT-CMC buck converter with a PI compensator is established. Based on this, the instability behaviors caused by output capacitance and feedback gain are investigated. Furthermore, an approximate instability condition is obtained and design-oriented stability boundaries in different circuit parameter spaces are yielded. The analysis results show that the instability of COT-CMC buck converters with a PI compensator is mainly affected by the output capacitance, output capacitor equivalent series resistance (ESR), feedback gain, current-sensing gain and constant on-time. The study results of this paper are helpful for the circuit parameter design of COT-CMC switching dc-dc converters. Experimental results are provided to verify the analysis results.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.677-687
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• 2018

This paper presents a novel power decoupling control scheme with the bidirectional buck-boost converter for primary-side regulation photovoltaic (PV) micro-inverter. With the proposed power decoupling control scheme, small-capacitance film capacitors are used to overcome the life-span and reliability limitations of the large-capacitance electrolytic capacitors. Then, an improved flyback PV inverter is employed in continuous conduction mode with primary-side regulation for the PV power conditioning. The proposed power-decoupling controller shares the reference for primary side current regulation of the flyback PV inverter. The decoupling controller shapes the input current of the bidirectional buck-boost converter. The shared reference eliminates the phase-delay between the input current to the bidirectional buck-boost converter and the double frequency current at the PV primary current. The elimination of the phase-delay in dynamic response enhances the ripple rejection capability of the power decoupling buck-boost converter even with small film capacitor. With proposed power decoupling control scheme, the additional advantage of the primary-side regulation of flyback PV inverter is that there is no need to have an extra current sensor for obtaining the ripplecurrent reference of the decoupling current-controller of the power-decoupling buck-boost converter. Therefore, the proposed power decoupling control scheme is cost-effective as well as the size benefit. A new transient analysis is carried out which includes the source voltage dynamics instead of considering the source voltage as a pure voltage source. For verification of the proposed control scheme, simulation and experimental results are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.6
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• pp.25-32
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• 2011

This paper proposes high efficiency current-mode DC-DC buck converter that are suitable for portable devices. The current-mode DC-DC buck converter using adjustable Dead-time control method improves the power efficiency 2~5%. The buck converter has been implemented with a standard 0.35${\mu}m$ CMOS process. The size of this chip is 0.97$mm^2$. The input range of the fabricated DC-DC buck converter is 2.5V~3.3V, and the output is 1.8V. The maximum loading current of the converter is 500mA and the peak efficiency is 93% at 200mA loads.

• Journal of IKEEE
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• v.15 no.4
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• pp.319-323
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• 2011

In this paper presents a new model of dual-mode synchronous buck converter with dynamic control for mobile applications was proposed. The proposed circuit can operate at 2.5MHz with supply voltage 2.5V to 5V for low ripple and minimum inductor and capacitor size, which is suitable for single-cell lithium-ion battery supply mobile applications. For high efficiency, the proposed circuit adopts synchronous type and dynamic control. The proposed circuit is designed by using the device parameter of TSMC 0.18um BCD process and the performance is evaluated by Cadence spectre. Experimental board level results show the maximum conversion efficiency is 96% at 100mA load current.