• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.6
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• pp.487-490
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• 2007

In this paper, the formation and thermal stability characteristics of Ni silicide using Ni-V alloy on Boron cluster ($B_{18}H_{22}$) implanted bulk and SOI substrate were examined in comparison with pure Ni for nano-scale CMOSFET. The Ni silicide using Ni-V alloy on $B_{18}H_{22}$ implanted SOI substrate after high temperature post-silicidation annealing showed the lower sheet resistance, no agglomeration interface image and lower surface roughness than that using pure Ni. The thermal stability of Ni silicide was improved by using Ni-V alloy on $B_{18}H_{22}$ implanted SOI substrate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.260-264
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• 2010

In this paper, Ni silicide is formed on boron cluster ($B_{18}H_{22}$) implanted source/drains for shallow junctions of nano-scale CMOSFETs and its thermal stability is improved, using vacuum annealing. Although Ni silicide on $B_{18}H_{22}$ implanted Si substrate exhibited greater sheet resistance than on the $BF_2$ implanted one, its thermal stability was greatly improved using vacuum annealing. Moreover, the boron depth profile, using vacuum post-silicidation annealing, showed a shallower junction than that using $N_2$ annealing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.3-4
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• 2006

본 논문에서는 nano-scale CMOSFET을 위해 Boron Cluster ($B_{18}H_{22}$)가 이온주입된 SOI 와 Bulk 기판들 이용하였으며 실리사이드의 열 안정성 개선을 위해 Ni-V을 증착한 것과 순수 Ni을 증착한 것을 비교 분석 하였다. 결과 SOI위에 Ni-V을 증착한 것이 제일 낮은 면 저항을 보여주었고 반대로 Bulk위에는 제일 높은 면 저항을 보여 주었다. 단면을 측정한 결과 SOI 위에 Ni-V을 증착한 동일 조건의 Ni보다 Silicide의 두께가 두껍게 형성된 것을 확인하였다.