• Journal of Electrical Engineering and Technology
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• v.6 no.4
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• pp.527-534
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• 2011

In the present paper, the characteristics of Mega-Flux$^{(R)}$, JNEX-Core$^{(R)}$, amorphous and ferrite cores are compared to the inductor of buck-boost converters for Hybrid Electric Vehicles. Core losses are analyzed at the condition of 10 kHz sine wave excitations, and permeability fluctuations vs. temperature and magnetizing force will be analyzed and discussed. Under the specifications of the buck-boost converter for 20 kW THS-II, the power inductor will be designed with Mega-Flux$^{(R)}$ and JNEX-Core$^{(R)}$, and informative simulation results will be provided with respect to dc bias characteristics, core and copper losses.

• Journal of Power Electronics
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• v.12 no.6
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• pp.912-924
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• 2012

In hybrid renewable power systems, the use of a multiple-input dc/dc converter (MIC) leads to simpler circuit and lower cost, when compared to the conventional use of several single-input converters. This paper proposed a novel three-input buck/boost/buck-boost converter, which can be used in applications with various values of input voltage. The energy sources in this converter can deliver power to the load either simultaneously or individually in one switching period. The steady relationship, the power management strategy and the small-signal circuit model of this converter have been derived. With decoupling technology, modeling and regulator design can be obtained under multi-loop control modes. Finally, three generating methods of a multiple-input buck/boost/buck-boost converter is given, and this method can be extended to the other multiple-input dc/dc converters.

• KEPCO Journal on Electric Power and Energy
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• v.7 no.2
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• pp.255-261
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• 2021

This paper proposes impedance-based stability analysis of DC-DC boost converters, where a harmonic state space (HSS) modeling technique is used. At first, the HSS model of the boost converter is developed. Then, the closed-loop output impedance of the converter is derived in frequency domain using small signal modeling including frequency couplings, where harmonic transfer function (HTF) matrices of the open-loop output impedance, the duty-to-output, and the voltage controller are involved. The frequency response of the output impedance reveals a resonance frequency at low frequency region and frequency couplings at sidebands of switching frequency which agree with the simulation and experimental result.

• Journal of Power Electronics
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• v.14 no.2
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• pp.237-248
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• 2014

Pulse-width modulated (PWM) full-bridge boost converters are used in applications where the output voltage is considerably higher than the input voltage. Zero-voltage-switching (ZVS) is typically implemented in these converters. A new ZVS-PWM full-bridge converter is proposed in this paper. The proposed converter does not have any of the disadvantages associated with other converters of this type, including a complicated auxiliary circuit, increased current stresses in the main power switches, and load-dependent ZVS operation. The operation of the proposed converter, its steady-state characteristics, and its design are explained and examined. The feasibility of the converter is confirmed with results obtained from an experimental prototype.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.143-149
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• 2016

The two-stage converter is widely used in traditional DC/AC inverter. It has several disadvantages such as complex topology, large volume and high loss. In order to overcome these shortcomings, a novel half load-cycle worked dual SEPIC single-stage inverter, which is based on the analysis of the relationship between input and output voltages of SEPIC converters operating in the discontinuous conduction mode (DCM), is presented in this paper. The traditional single-stage inverter has remarkable advantages in small and medium power applications, but it can’t realize boost DC/AC output directly. Besides one pre-boost DC/DC converter is needed between the DC source and the traditional single-stage inverter. A novel DC/AC inverter without pre-boost DC/DC converter, which is comprised of two SEPIC converters, is studied. The output of dual SEPIC converters is connected with anti-parallel and half load-cycle control is used to realize boost and buck DC/AC output directly and work properly, whatever the DC input voltage is higher or lower than the AC output voltage. The working principle, parameter selection and the control strategy of the inverters are analyzed in this paper. Simulation and experiment results verify the feasibility of the new inverter.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1689-1697
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• 2016

Continuous conduction mode (CCM) boost converters are commonly used in home appliances and various industries because of their simple topology and low input current ripples. However, these converters suffer from several disadvantages, such as hard switching of the active switch and reverse recovery problems of the output diode. These disadvantages increase voltage stresses across the switch and output diode and thus contribute to switching losses and electromagnetic interference. A new topology is presented in this work to improve the switching characteristics of CCM boost converters. Zero-current turn-on and zero-voltage turn-off are achieved for the active switches. The reverse-recovery current is reduced by soft turning-off the output diode. In addition, an input current sensorless control is applied to the proposed topology by pre-calculating the duty cycles of the active switches. Power factor correction is thus achieved with less effort than that required in the traditional method. Simulation and experimental results verify the soft-switching characteristics of the proposed topology and the effectiveness of the proposed input current sensorless control.

• Journal of Power Electronics
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• v.10 no.2
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• pp.132-137
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• 2010

Interleaving techniques are widely used to reduce input/output ripples and to increase the power capacity of boost converters operating in critical conduction mode. Two types of phase-shift control schemes are studied in this paper, the turn-on time shifting method and the turn-off time shifting method. It is found that although the turn-off time shifting method exhibits better performance, it suffers from sub-harmonic oscillations at high input voltages. To solve this problem, an intensive quantitative analysis of the sub-harmonic oscillation phenomenon is made in this paper. Based upon that, a novel modified turn off time shifting control scheme for interleaved boost converters operating in critical conduction mode is proposed. An important advantage of this scheme is that both the master phase and the slave phase can operate stably in critical conduction mode without any oscillations in the full input voltage range. This method is implemented with a FPGA based digital PWM control platform, and tests were carried out on a two-phase interleaved boost PFC converter prototype. Experimental results demonstrated the feasibility and performance of the proposed phase-shift control scheme.

• Journal of Power Electronics
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• v.15 no.3
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• pp.577-586
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• 2015

The combination of voltage feedforward and feedback control is a conventional approach for correcting the power factor in single-phase ac-dc boost converters. The feedback duty ratio increases significantly with an increase of the line frequency and input inductance. Therefore, the performance of the conventional approach is highly dependent on the bandwidth of the feedback controller. As a result, the input power quality can be significantly exacerbated due to uncompensated duty ratios if the feedback controller is limited. This paper proposes an input impedance and current feedforward control method to reduce the control portion of the feedback controller. The findings in this paper are 1) the theoretical derivation and analysis of variations of line frequency and input inductance on a power factor correction approach, 2) guaranteed consistent performance in a wide range of conditions, and 3) that a low switching frequency can be utilized by the proposed method. A MATLAB/Simulink model and a 1.2kW dual boost converter are built to demonstrate the effectiveness of the proposed method.

• Journal of IKEEE
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• v.16 no.3
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• pp.203-210
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• 2012

Since the non-overlapping gate driver used in conventional DC-DC boost converters generates fixed dead-times, the converters suffer from the body-diode conduction loss or the charge-sharing loss. To reduce the efficiency degradation due to these losses, this paper presents a PWM DC-DC boost converter with adaptive dead-time control. The proposed DC-DC boost converter delivering 3.3V output from a 2.5V input is designed with CMOS $0.3{\mu}m$ technology. It operates at 500kHz and has a maximum power efficiency of 97.3%.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.1
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• pp.53-58
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• 2021

Operation of the interleaved Boost PFC converter in Critical Conduction Mode (CrM) shows the advantages of high efficiency and good EMI characteristics owing to the valley switching of FET. However, when it is designed for a highly pulsating load, operation at a relatively high frequency is inevitable at non-pulsating typical load condition, resulting in efficiency degradation. Moreover, the physical size of the inductor becomes problematic because of the nature of the CrM operation, where the inductor peak current is about two times the inductor average current, thereby requiring high DC-bias characteristics, which is worse when the output power is high. In this study, a new parallel driving method of two sets of interleaved boost PFC converters for highly pulsating high-power application is proposed. The proposed method does not require any additional load-sharing controller, resulting in high efficiency and smaller inductor size.