• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.5
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• pp.195-200
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• 2009

CRT-based RSA algorithm, which was implemented on smartcard, microcontroller and so on, leakages secret primes p and q by fault attacks using laser injection, EM radiation, ion beam injection, voltage glitch injection and so on. Among the many fault injection methods, voltage glitch can be injected to target device without any modification, so more practical. In this paper, we made an experiment on the fault injection attack using abnormal source voltage. As a result, CRT-RSA's secret prime p and q are disclosed by fault attack with voltage glitch injection which was introduced by several previous papers, and also succeed the fault attack with source voltage blocking for proper period.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.330-334
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• 1999

This paper presents a new transient voltage blocking device (TBD) for commucation facilities with low power and high frequency bandwidth. Conventional protection devices have some problems such as low frequency bandwidth, low energy capacity and high remnant voltage. In order to improve these limitations, the new TBD, which consists of a gas tube, avalanche diodes and junction type field effect transistors (JFETs), was designed and fabricated JFETs were used as an active non-linear element and a high speed switching diode with low capacitance limits high current. Therefore the avalanche diodes with low energy capacity are protected from the high current, and the TBD has a very small input capacitance. From the performance test using surge generator, which can produce 1.2/50${\mu}\textrm{s}$ 4.2 k$V_{max}$, 8/20${\mu}\textrm{s}$ 2.1 kA$\sub$max/, it is confirmed that the proposed TBD has an excellent protection performance in tight clamping voltage and limiting current characteristics.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.2
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• pp.94-102
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• 2020

Considering that the output voltage and current of a single PV panel are limited in PV power generation, a PV array should be constructed by connecting several PV panels in series and parallel to meet the required voltage/power levels for power generation capacity. When a PV array is partially shaded, the maximum power generation depends on the configuration of a PV array and the presence or absence of blocking diodes. This study considers six PV array configurations and the presence or absence of blocking diodes. An optimum connection structure was proposed to maximize power generation in a partial shadow condition. Results were verified through simulation and an experiment.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1486-1495
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• 2019

Dealing with the DC link fault poses a technical problem for an HVDC based on a modular multilevel converter. The fault suppressing mechanisms of several sub-module topologies with DC fault current blocking capacity are examined in this paper. An improved half-bridge sub-module topology with double direction control switch is also designed to address the additional power consumption problem, and a sub-module topology called hybrid double direction blocking sub module (HDDBSM) is proposed. The DC fault suppression characteristics and sub-module capacitor voltage balance problem is also analyzed, and a self-startup method is designed according to the number of capacitors. The simulation model in PSCAD/EMTDC is built to verify the self-startup process and the DC link fault suppression features.

• Journal of Power Electronics
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• v.19 no.1
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• pp.68-78
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• 2019

The emergence of high voltage conversion applications has resulted in a trend of using semiconductor device series associations. Series associations allow for operation at blocking voltages, which are higher than the nominal voltage for each of the semiconductor devices. The main challenge with these topologies is finding a way to guarantee the voltage balance between devices in both blocking and switching transients. Most of the methods that have been proposed to mitigate static and dynamic voltage unbalances result in increased losses within the device. This paper introduces a new series stack topology, where the voltage unbalances are reduced. This in turn, mitigates the switching losses. The proposed topology consists of a circuit that ensures the soft switching of each device, and one auxiliary circuit that allows for switching energy recovery. The principle for the topology operation is presented and experimental tests are performed for two modules. The topology performs excellently for switching transients on each of the devices. The voltage static unbalances were limited to 10%, while the activation/deactivation delay introduced by the lower module IGBT driver takes place in the dynamic unbalances. Thus, the switching losses are reduced by 40%, when compared to hard switching configurations.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.727-736
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• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.

• Journal of Sensor Science and Technology
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• v.2 no.1
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• pp.29-34
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• 1993

a-Si : H photodiodes for image sensor have been fabricated and characterized. Photosensitivity of a ITO/a-Si : H/Al photodiode without blocking layer was 0.7 under the applied voltage of 5 V and peak spectral sensitivity in visible region was found at 620 nm. Dark current of ITO/a-SiN : H/a-Si : H/p-a-Si : H/Al photodiode was suppressed by hole blocking layer and electron blocking layer at the value of lower than 1.5 pA to the applied voltage of 10 V. Also maximum photosensitivity was about 1 under the applied voltage of 3 V and peak spectral sensitivity was found at 540 nm.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.219-219
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• 2013

The effect of an electron blocking layer (EBL) on V-I curves in GaN/InGaN multiple quantum well is investigated. For the first time, we found that curves were intersected at 3.012 V and analyzed the reason for intersection. The forward voltage in LEDs with an p-AlGaN EBL is larger than without p-AlGaN EBL at low injection current because the Mg doping efficiency for p-GaN layer was higher than that of p-AlGaN layer. However, the forward voltage in LEDs with an p-AlGaN EBL is smaller than without p-AlGaN EBL at high injection current because the carriers overflow from the active layer when injection current increases in LEDs without p-AlGaN EBL and in case of LED with p-AlGaN EBL, the carriers are blocked by EBL.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1148-1151
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• 2005

Photovoltaic effects in organic solar cell were studied in a cell configuration of ITO/PEDOT:PSS/CuPc(20 nm)/$C_{60}$(40 nm)/BCP/Al(150 nm) at room temperature. Here, the BCP layer works as an exciton blocking layer. The exciton blocking layer must transport electrons from the acceptor layer to the metal cathode with minimal increase in the total cell series resistance and should absorb damage during cathode deposition. Therefore, a proper thickness of the exciton blocking layer is required for an optimized photovoltaic cell. Several thicknesses of BCP were made between $C_{60}$ and Al. And we obtained characteristic parameters such as short-circuit current, open-circuit voltage, and power conversion efficiency of the device under the illumination of AM 1.5.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.273-274
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• 2005

Photovoltaic effects in organic solar cell were studied in a cell configuration of ITO/PEDOT:PSS/CuPc(20nm)/$C_{60}$(40nm)/BCP/Al(150nm) at room temperature. Here, the BCP layer works as an exciton blocking layer. The exciton blocking layer must transport electrons from the acceptor layer to the metal cathode with minimal increase in the total cell series resistance and should absorb damage during cathode deposition. Therefore, a proper thickness of the exciton blocking layer is required for an optimized photovoltaic cell. Several thicknesses of BCP were made between $C_{60}$ and Al. And we obtained characteristic parameters such as short-circuit current, open-circuit voltage, and power conversion efficiency of the device under the illumination of AM 1.5.