• Title/Summary/Keyword: Block layout

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A space partitioning method embedded in a simulated annealing algorithm for facility layout problems with shape constraints

  • Kim, Jae-Gon;Kim, Yeong-Dae
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 1996.04a
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    • pp.465-468
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    • 1996
  • We deal with facility layout problems with shape constraints. A simulated annealing algorithm is developed for the problems. In the algorithm, a solution is encoded as a matrix that has information about relative locations of the facilities in the floor. A block layout is constructed by partitioning the floor into a set of rectangular blocks according to the information while satisfying areas of facilities. In this paper, three methods are suggested for the partitioning procedure and they are employed in the simulated annealing algorithm. Results of computational experiments show that the proposed algorithm performs better than existing algorithms, especially for problems with tight shape constraints.

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Optimal Two-Section Layouts for the Two-Dimensional Cutting Problem

  • Ji, Jun;Huang, Dun-hua;Xing, Fei-fei;Cui, Yao-dong
    • Journal of Information Processing Systems
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    • v.17 no.2
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    • pp.271-283
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    • 2021
  • When generating layout schemes, both the material usage and practicality of the cutting process should be considered. This paper presents a two-section algorithm for generating guillotine-cutting schemes of rectangular blanks. It simplifies the cutting process by allowing only one size of blanks to appear in any rectangular block. The algorithm uses an implicit enumeration and a linear programming optimal cutting scheme to maximize the material usage. The algorithm was tested on some benchmark problems in the literature, and compared with the three types of layout scheme algorithm. The experimental results show that the algorithm is effective both in computation time and in material usage.

A Study on the Layout Patterns of Public Schools in Manhattan - Focused on Relationship between Manhattan Grid Plan and Open Space - (뉴욕시 공립학교에 나타난 배치 특성에 관한 연구 - 맨하튼 가로체계와 외부공간의 관계를 중심으로 -)

  • Kim, Pil-Soo;Jeon, You-Chang
    • Journal of the Korean Institute of Educational Facilities
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    • v.20 no.2
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    • pp.3-14
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    • 2013
  • The purpose of this study is to analyze patterns of public school building layout types, open space and relationship with communities in the Manhattan grid plan. The study illustrates how building layout patterns of school facilities are influenced by societal demands in the urban grid environment. During the nineteenth century, the Island of Manhattan was transformed into a physical representation of the Cartesian coordinate system via the development of the grid street plan. In order to take advantage of streets as urban space, it is quite important to understand characteristics of communities and open space relationships between buildings and streets. Moreover, the strategic planning of schools' outdoor space vitalizes public streets as a critical community anchor. This research reviews 118 Manhattan public schools and categorizes them by (1) building layout type, (2) site type, (3) circulation and public open space, which are the biggest factors that determine the layout patterns of the public schools in Manhattan. As a result of analysis, the layout patterns are classified into seven types : "ㅡ", "L", "ㄷ", "ㅁ", "H", "T" and "other" type. Of these, "ㅡ" type and "L" type occur most frequently, because these configurations most flexibly fit into the limited grid-locked blocks, the various types of site & topography, and adapt most dynamically to the open spaces created by using avenues and streets. The ultimate objective of this study is to provide a case study for future efforts to plan open spaces for campuses that effectively utilize the streets in proximity.

The Block Segmentation and Extraction of Layout Information In Document (문서의 영역분리와 레이아웃 정보의 추출)

  • 조용주;남궁재찬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.17 no.10
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    • pp.1131-1146
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    • 1992
  • In this paper, we suggest a new algorithm applied to the segmentation of published documents to obtain constituent and layout information of document. Firstly, we begin the process of blocking and labeling on a 300dpi scanned document. Secondly, we classify the blocked document by individual sub-regions. Thirdly, we group sub-regions into graphic areas and text areas. Finally, we extract information for layout recognition by using the data. From an experiment on papers of an academic society, we obtain the above 98% of region classification rate and extraction rate of information for the layout recognition.

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The Block-Based Storage Policy and Order Processing in Logistics Warehouse (물류창고에서 블록별 저장방식 및 주문 처리에 관한 연구)

  • 김명훈;김종화
    • Journal of the Korea Society of Computer and Information
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    • v.8 no.4
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    • pp.159-164
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    • 2003
  • Location of stock in a warehouse directly affects the total materials handling expense of all goods moving through the warehouse. The purpose of this paper is to develop a storage policy in order picking warehouse, the block-based storage policy to minimize the total order picking time. In block-based storage policy, the rack is divided into blocks and items are assigned to each block based on the turn-over rate of each item and the average distance between the blocks and the dock. To demonstrate the performance of the proposed policy, we compare with the existing method called class-based storage policy under various matching methods.

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Facility Layout Problem with Genetic Algorithm (Genetic Algorithm을 이용한 건설물자재의 Layout)

  • Jang Hyoun-Seung
    • Proceedings of the Korean Institute Of Construction Engineering and Management
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    • autumn
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    • pp.99-103
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    • 2003
  • The most commonly used method for space management in the industry is development of site plans. These plans outline how to manage material deliveries, staging areas, and crane locations for construction sites in suburban area but not in congested urban areas. This study focuses on how to efficiently manage space for construction facilities on high-rise buildings in congested urban areas where normally space for facilities around a building footprint is not available. The limitations of available horizontal space create a need to explore vertical expansion of facilities. This raises new aspects of vertical facility handling and flow that need to be considered in the facility design problem. The construction facilities layout plan method provides layout planners with a valuable technique to develop efficient sequences of work that optimally defines how to efficiently utilize the construction facilities and minimize the travel of specific facilities effort on multiple-floor buildings. A genetic algorithm-based heuristic will be presented for generating block layouts for multiple-floor la)rout problems.

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Analysis of the Disposal Tunnel and Disposal Pit Spacing for the Spent Fuel Repository Layout (사용후핵연료 지하 처분장 배치를 위한 처분공 및 처분터널 간격 분석)

  • Lee, Jong-Youl;Lee, Yang;Choi, Heui-Joo;Choi, Jong-Won
    • Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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    • v.4 no.4
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    • pp.393-400
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    • 2006
  • In design of a deep geological repository for the high level wastes, it is very important that the temperature of the bentonite block should not be over $100^{\circ}C$ to maintain the integrity of the bentonite buffer block from the decay heat. In this study, for the layout of the repository to meet the requirement, the analysis of the disposal tunnel and disposal pit spacing was carried out. To do this, based on the reference repository concept, several cases of cooling times and disposal tunnel and disposal pit spacing were compared. The thermal stabilities of the disposal systems were analyzed in terms of the cooling time and spacing. The results showed that it was more desirable to determine the layout of the repository in terms of disposal pit spacing than the disposal tunnel spacing. The results of these analyses can be used in the deep geological repository design. The detailed analyses with the exact site characteristics data will reduce the uncertainty of the results.

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A Block Disassembly Technique using Vectorized Edges for Synthesizing Mask Layouts (마스크 레이아웃 합성을 위한 벡터화한 변을 사용한 블록 분할 기법)

  • Son, Yeong-Chan;Ju, Ri-A;Yu, Sang-Dae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.12
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    • pp.75-84
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    • 2001
  • Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.

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Design of Dynamic Time Warp Element for Speech Recognition (음성인식을 위한 Dynamic Time Warp 소자의 설계)

  • 최규훈;김종민
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.3
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    • pp.543-552
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    • 1994
  • Dynamic Time Warp(DTW) needs for iterative calculations and the design of PE cell suitable for the operations is very important. Accordingly, this paper aims at real time recognition design enables large dictionary hardware realization using DTW algorithm. The DTW PE cell separated into three large blocks. "MIN" is the one block for counting accumulated minimum distance. "ADD" block calculates these minimum distances, and "ABS" seeks for the absolute values to the total sum of local distances. Circuit design and verification about the three block have been accomplished, and performed layout '||'&'||' DRC(design rule check) using 1.2 m CMOS N-Well rule base.CMOS N-Well rule base.

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A real-time high speed full search block matching motion estimation processor (고속 실시간 처리 full search block matching 움직임 추정 프로세서)

  • 유재희;김준호
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.12
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    • pp.110-119
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    • 1996
  • A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

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