• Title/Summary/Keyword: Block device

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Study on the Performance Verification of PRB Isolation Device using Simulation and Experiment (PRB 지진격리장치의 성능 검증을 위한 해석 및 실험적 연구)

  • Kim, Sung-Jo;Kim, Se-Yun;Ji, Yongsoo;Kim, Bongsik;Han, Tong-Seok
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.33 no.5
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    • pp.311-318
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    • 2020
  • This study introduces a technique for improving the elastomeric-isolator performance using modular devices. The modular devices are shear resistance block, polymer spring, displacement acceptance guide, and anti-falling block. They are installed on the elastomeric isolator as a supplementary device. Each modularized device improves the isolator performance by performing step-by-step actions according to the seismic intensity and displacement. The PRB isolation device works in four stages, depending on the seismic magnitude, to satisfy the target performance. It is designed to accommodate design displacement in the first stage and large magnitude of earthquakes in the second and third stages. This design prevents superstructures from falling in the fourth stage due to large-magnitude earthquakes by increasing the capacity limit of the elastomeric isolator. In this study, the PRB isolation device is analyzed using finite element analysis to verify that the PRB isolation device works as intended and it can withstand loads corresponding to large-magnitude earthquakes. The performance of the PRB isolation device is validated by the analysis, which is further corroborated by actual experiments.

Design of Encryption/Decryption Core for Block Cipher HIGHT (블록 암호 HIGHT를 위한 암·복호화기 코어 설계)

  • Sonh, Seung-Il
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.4
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    • pp.778-784
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    • 2012
  • A symmetric block cryptosystem uses an identical cryptographic key at encryption and decryption processes. HIGHT cipher algorithm is 64-bit block cryptographic technology for mobile device that was authorized as international standard by ISO/IEC on 2010. In this paper, block cipher HIGHT algorithm is designed using Verilog-HDL. Four modes of operation for block cipher such as ECB, CBC, OFB and CTR are supported. When continuous message blocks of fixed size are encrypted or decrypted, the desigend HIGHT core can process a 64-bit message block in every 34-clock cycle. The cryptographic processor designed in this paper operates at 144MHz on vertex chip of Xilinx, Inc. and the maximum throughput is 271Mbps. The designed cryptographic processor is applicable to security module of the areas such as PDA, smart card, internet banking and satellite broadcasting.

An Efficient Hardware Implementation of Block Cipher CLEFIA-128 (블록암호 CLEFIA-128의 효율적인 하드웨어 구현)

  • Bae, Gi-Chur;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.05a
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    • pp.404-406
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    • 2015
  • This paper describes a small-area hardware implementation of the block cipher algorithm CLEFIA-128 which supports for 128-bit master key. A compact structure using single data processing block is adopted, which shares hardware resources for round transformation and the generation of intermediate values for round key scheduling. In addition, data processing and key scheduling blocks are simplified by utilizing a modified GFN(generalized Feistel network) and key scheduling scheme. The CLEFIA-128 crypto-processor is verified by FPGA implementation. It consumes 823 slices of Virtex5 XC5VSX50T device and the estimated throughput is about 105 Mbps with 145 MHz clock frequency.

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A VLSI DESIGN OF CD SIGNAL PROCESSOR for High-Speed CD-ROM

  • Kim, Jae-Won;Kim, Jae-Seok;Lee, Jaeshin
    • Proceedings of the IEEK Conference
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    • 2002.07b
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    • pp.1296-1299
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    • 2002
  • We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.[2]So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

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Wear Leveling Technique using Bit Array and Bit Set Threshold for Flash Memory

  • Kim, Seon Hwan;Kwak, Jong Wook;Park, Chang-Hyeon
    • Journal of the Korea Society of Computer and Information
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    • v.20 no.11
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    • pp.1-8
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    • 2015
  • Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

Selection and implementation of Standard Functional Blocks for Radio Library in multi-mode mobile device (멀티모드 단말기의 라디오 라이브러리를 위한 표준 기능 블록의 선정 및 구현)

  • Jung, Ildo;Choi, Sengwon
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.12 no.3
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    • pp.125-132
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    • 2016
  • The European Telecommunication Standards Institute (ETSI) Technical Committee (TC) Reconfigurable Radio Systems (RRS) is standardizing the multi-mode Mobile Device (MD). The configuration of multi-mode MD is determined by the downloaded mobile communication standard software. In this paper, we introduce the Radio Library concept for multi-mode MD which is one of the key components of RRS standard. This paper also introduces the Standard Functional Block which is a part of Radio Library. A method for selecting efficiency SFBs for multi-mode MD is presented and a Radio Library is generated based on the selected SFBs. This paper also shows sample Standard Functional Block Set which included in Radio Library. In order to verify the compatibility of the generated Radio Library which was made by C language, we implement the LTE Rel-10 and Wi-Fi(802.11b) to show the efficiency of generating a mobile communication standard software based on the Radio Library. Then using the Prograph Visual Programming MartenTM 1.6.4, we compiled our LTE Rel-10 and Wi-Fi(802.11b) source code.

The characteristic of leakage current in ZnO surge arrestor elements with mixed direct and 60Hz voltage (중첩전압(직류+교류 60Hz)에서 산화아연 피뢰기 소자의 누설전류 특성)

  • Lee, B.H.;Pak, K.Y.;Kang, S.M.;Choi, H.S.;Oh, S.K.
    • Proceedings of the KIEE Conference
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    • 2003.10a
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    • pp.186-188
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    • 2003
  • The ZnO surge arrester is the protective device for limiting surge voltages on equipment by diverting surge current and returning the device to its original status. The occurrence of overvoltage appears in any phase to AC power supply system and it appears in mixing AC and impulse voltages, moreover because HVDC power supply system uses converter in semiconductor, it makes mixed DC and high harmonics voltages. In this study, the various mixed AC and DC voltages was made for investigating the degradation effect of ZnO arrester according to mixed voltage. As a result, the increase of DC component to mixed voltages causes the increase of resistive component of total leakage current to ZnO block. In changing V-I curve for mixed voltages, the cross-over point acts a factor as making the proper capacitor size of an equivalent circuit for ZnO block.

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Sliding Mode Observer Driver IC Integrated Gate Driver for Sensorless Speed Control of Wide Power Range of PMSMs

  • Oh, Jimin;Kim, Minki;Heo, Sewan;Suk, Jung-Hee;Yang, Yil Suk;Park, Ki-Tae;Kim, Jinsung
    • ETRI Journal
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    • v.37 no.6
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    • pp.1176-1187
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    • 2015
  • This work proposes a highly efficient sensorless motor driver chip for various permanent-magnet synchronous motors (PMSMs) in a wide power range. The motor driver chip is composed of two important parts. The digital part is a sensorless controller consisting mainly of an angle estimation block and a speed control block. The analog part consists of a gate driver, which is able to sense the phase current of a motor. The sensorless algorithms adapted in this paper include a sliding mode observer (SMO) method that has high robust characteristics regarding parameter variations of PMSMs. Fabricated SMO chips detect back electromotive force signals. Furthermore, motor current-sensing blocks are included with a 10-bit successive approximation analog-to-digital converter and various gain current amplifiers for proper sensorless operations. Through a fabricated SMO chip, we were able to demonstrate rated powers of 32 W, 200 W, and 1,500 W.

A Non-volatile Memory Lifetime Extension Scheme Based on the AUTOSAR Platform using Complex Device Driver (AUTOSAR 플랫폼 기반 CDD를 활용한 비휘발성 메모리 수명 연장 기법)

  • Shin, Ju-Seok;Son, Jeong-Ho;Lee, Eun-Ryung;Oh, Se-Jin;Ahn, Kwang-Seon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.8 no.5
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    • pp.235-242
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    • 2013
  • Recently, the number of automotive electrical and electronic system has been increased because the requirements for the convenience and safety of the drivers and passengers are raised. In most cases, the data for controlling the various sensors and automotive electrical and electronic system used in runtime should be stored on the internal or external non-volatile memory of the ECU(Electronic Control Units). However, the non-volatile memory has a constraint with write limitation due to the hardware characteristics. The limitation causes fatal accidents or unexpected results if the non-volatile memory is not managed. In this paper, we propose a management scheme for using non-volatile memory to prolong the writing times based on AUTOSAR(AUTOmotive Open System Architecture) platform. Our proposal is implemented on the CDD(Complex Device Driver) and uses an algorithm which swaps a frequently modified block for a least modified block. Through the development of the prototype, the proposed scheme extends the lifetime of non-volatile memory about 1.08 to 2.48 times than simply using the AUTOSAR standard.