• Journal of the Korean Society for Precision Engineering
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• v.11 no.6
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• pp.65-74
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• 1994

Various substructure synthesis methods, such as component mode synthesis, building block analysis and reduced impedance method, are studied for the determination of vibration characteristics of plate problems. Comparisons are made for each methods in terms of accuracy and computational efficiency. Following conclusions are made from the results of computer simulations and experiments. i) The computation time of component mode synthesis is much shorter than that of whole structure analysis. The natural frequencies of lower modes obtained from component mode synthesis are almost same as those obtained from whole structure analysis, but in higher modes the differences between those two methods are increases. ii) The transfer function obtained from building block analysis is same as that obtained from the finite element method. iii) Same transfer functions can be obtained by the reduced impedance method. The computation time of reduced impedance mathod is shorter that that of general finite element method, but for the solutions in broad frequency band it requires long calculation time.

• Proceedings of the KSR Conference
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• 2004.06a
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• pp.1247-1252
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• 2004

ATC(Automatic Train Control) system employed in Bundang urban transit is operated in accordance with automatic blocking equipment. Using AF(Audio Frequency) track circuits installed at a block section, the block signal is automatically controlled and the safety of train operation is supported. In this paper, we investigate the operation mode of bundang urban transit and analyze the operation algorithm of ATC on-board system.

• Journal of the military operations research society of Korea
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• v.10 no.2
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• pp.61-73
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• 1984

A block replacement policy using items with different reliability is discussed. We divide system unit failure modes into two modes and use less reliable unit when operating unit fails near the planned preventive replacement time. In this policy, item A has two failure modes. Mode-1 failure is removed by minimal repair, mode-2 failure by replacement. If mode-2 failure of item A happens in (0, $T-{\delta}$), failure item A is replaced by new item A. If mode-2 failure of item A happens in ($T-{\delta}$, T), failure item A is replaced by new item B. Item B should be cheaper and less durable than item A. Under this policy, we determine the preventive replacement interval $T^{*}$ and the interval ${\delta}^{*}$ of item B replacement which minimize the cost rate per unit time.

• ETRI Journal
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• v.6 no.3
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• pp.17-20
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• 1984

A block replacement policy using items with different reliability is discussed. We devide system unit failure modes into two modes and use less reliable unit when operating unit fails near the planned preventive replacement time. In this policy, item A has two failure modes. Mode-1 failure is removed by minimal repair, mode-2 failure by replacement. If mode-2 failure of item A happens in (0,T- $\delta$). failure item A is replaced by new item A. If mode-2 failure of item A happens in(T-$\delta$,T), failure item A is replaced by new item B. Item B should be cheaper and less durable than item A. Under this policy, we determine the preventive replacement interval T and the interval $\delta$ of item B replacement which minimize the cost rate per unit time.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.323-326
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• 2016

High Efficiency Video Coding (HEVC) adopts intra transform skip mode, in which a residual block is directly quantized in the pixel domain without transforming the block into the frequency domain. Intra transform skip mode provides a significant coding gain for screen content. However, when intra-prediction errors are not transformed, the errors are often correlated along the intra-prediction direction. This paper introduces a residual differential pulse code modulation (DPCM) method for the intra-predicted and transform-skipped blocks to remove redundancy. The proposed method performs pixel-by-pixel residual prediction along the intra-prediction direction to reduce the dynamic range of intra-prediction errors. Experimental results show that the transform skip mode's Bjøntegaard delta rate (BD-rate) is improved by 12.8% for vertically intra-predicted blocks. Overall, the proposed method shows an average 1.2% reduction in BD-rate, relative to HEVC, with negligible computational complexity.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2007.05a
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• pp.437-439
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• 2007

This paper was analyzed the resistivity change characteristic of mortar model block and concrete that was made earth electrode that's used concrete or basic concrete of building for 1 year. The early resistivity measurement value of concrete model block is higher than mortar model block. But after 1 year the resistivity measurement value of mortar model block is significantly higher than concrete model block. Because depends on time elapsed complete dryness factor of mortar model block that has not gravel is higher than concrete model block. And absorptance and function of mortar mode block was by far outstanding than concrete model block in the data for verification of the amount of contained water and the amount of dryness of mortar model block and concrete model block.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.1-6
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• 2005

This paper proposes a high performance multiplier using CMOS multiple-valued logic circuits. The multiplier based on the Modified Baugh-Wooley algorithm is designed with current-mode CMOS quaternary logic circuits. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion block), current-mode quaternary logic full-adder block, and quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. This multiplier can easily adapted to the binary system by the encoder and the decoder. This circuit is designed with 0.35um standard CMOS process at 3.3V supply voltage and 5uA unit current. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.4
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• pp.588-594
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• 2021

SIMON, a lightweight block cipher developed by the US National Security Agency, is a family of block ciphers optimized for hardware implementation. It supports many kinds of standards to operate in various environments. The counter mode of operation is one of the operational modes. It provides to encrypt plaintext which is longer than the original size. The counter mode uses a constant(Nonce) and Counter value as an input value. Since Nonce is the identical for all blocks, so it always has same result when operates with other constant values. With this feature, it is possible to skip some instructions of round function by pre-computation. In general, the input value of SIMON is affected by the counter. However in an 8-bit environment, it is calculated in 8-bit units, so there is a part that can be pre-computed. In this paper, we focus the part that can be pre-calculated, and compare with previous works.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.141-146
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• 2016

HEVC/H.265 is the latest joint video coding standard proposed by ITU-T SG 16 WP and ISO/IEC JTC 1/SC29/WG 11. In H.265, pictures are divided into a sequence of coding tree units(CTUs), and the CTU further is partitioned into multiple CUs to adapt to various local characteristics. Its coding efficiency is approximately two times high compared to previous standard H.264/AVC. However according to the size of extended CU(coding unit) and transform block, the hardware size of PMR(prediction/mode decision/reconstruction) block within video encoder is about 4 times larger than previous standard. In this study, we propose a new less complex hardware architecture of PMR block which has the most high complexity within encoder without any noticeable PSNR loss. Using this simplified block, we can shrink the overall size the H.265 encoder. For FHD image, it operates at clocking frequency of 300 MHz and frame rate of 60 fps. And also for the test image, the Bjøntegaard Delta (BD) bit rate increase about average 30 % in PMR prediction block, and the total estimated gate count of PMR block is around 1.8 M.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.6
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• pp.1217-1223
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• 2020

The Block cipher CHAM is lightweight block cipher for low-end processors, developed by National Security Research Institute from Korea. The mode of operation is necessity for efficient operation of block cipher, among them, the counter (CTR) mode has good efficiency because it is easy to implement and supporting parallel operation. In this paper, we propose the optimized implementation for block cipher CHAM-CTR. The proposed implementation can be skipped some rounds by pre-computation. Thus it has better calculating speed than existing CHAM. Also, this implementation pre-load some of round keys to registers, before entering round functions. It makes reduced 160cycles loading time for round key load. Finally, proposed implementation achieved higher performance about 6.8%, and 4.5% for fixed-key scenario, and variable-key scenario, respectively.