• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.3
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• pp.349-356
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• 2020

GIFT is a PRESENT-like cryptographic algorithm proposed in CHES 2017 and used S-box that can be implemented through a bit-slice technique[1]. Since bit-permutation is used as a linear layer, it can be efficiently implemented in hardware, but bit-slice implementation in software requires a specific conversion process, which is costly. In this paper, we propose a new bit-permutation that enables efficient bit-slice implementation and GIFT-64-variant using it. GIFT-64-variant has better safety than the existing GIFT in terms of differential and linear cryptanalysis.

• Convergence Security Journal
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• v.10 no.2
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• pp.19-26
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• 2010

In this study, we try to make up for the vulnerability in steganography that it is easily revealed the hidden logo image in cover image by bit-plane extraction. For this, we apply some methods, the permutation which shift the scattered pieces of logo image to one side, bit-plane dispersion insertion method and pack-type compressor.

• ETRI Journal
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• v.29 no.6
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• pp.820-822
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• 2007

ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area-efficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128-bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.183-191
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• 2023

Cryptographic algorithms require extensive computational resources and rely on complex mathematical principles for security. However, IoT devices have limited resources, leading to insufficient computing power. As a result, lightweight cryptography has emerged, which uses fewer computational resources. NIST organized a competition to standardize lightweight cryptography and TinyJAMBU, one of the algorithms in the competition, is a permutation-based algorithm that repeats many permutation operations. In this paper, we implement TinyJAMBU on an 8-bit AVR processor with a proposedtechnique that includes a reverse shift method and precomputing some operations in a fixed key and nonce environment. Our techniques showed a maximum performance improvement of 7.03 times in permutation operations and 5.87 times in the TinyJAMBU algorithm, improving up to 9.19 times in a fixed key and nonce environment.

• Journal of Communications and Networks
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• v.10 no.1
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• pp.79-88
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• 2008

In this paper, we propose efficient peer assignment algorithms for low-latency transmission of scalable coded images in peer-to-peer networks, in which peers may dynamically join and leave the networks. The objective of our algorithm is to minimize the transmission time of a requested image that is scalable coded. When an image is scalable coded in different bit rates, the bit stream encoded in a lower bit rate is a prefix subset of the one encoded in a higher bit rate. Therefore, a peer with the same requested image coded in any bit rate, even when it is different from the requested rate, may work as a supplying peer. As a result, when a scalable coded image is requested, more supplying peers can be found in peer-to-peer networks to help with the transfer. However, the set of supplying peers is not static during transmission, as the peers in this set may leave the network or finish their transmission at different times. The proposed peer assignment algorithms have taken into account the above constraints. In this paper, we first prove the existence of an optimal peer assignment solution for a simple identity permutation function, and then formulate peer assignment with this identity permutation as a mixed-integer programming problem. Next, we discuss how to address the problem of dynamic peer departures during image transmission. Finally, we carry out experiments to evaluate the performance of proposed peer assignment algorithms.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.1
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• pp.99-107
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• 2005

ARIA is a 128-bit block cipher having 128-bit, 192-bit, or 256-bit key length. The cipher is a substitution and permutation encryption network (SPN) and uses an involutional binary matrix. This structure was efficiently developed into light weight environments or hardware implementations. This paper shows that a careless implementation of an ARIA on smartcards is vulnerable to a differential power analysis attack This attack is realistic because we can measure power consumption signals at two kinds of S-boxes and two types of substitution layers. By using the two round key, we extracted the master key (MK).

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.6 no.2
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• pp.75-84
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• 2002

Using good properties of an optimal normal basis of type I in a finite field ${\mathbb{F}}_{2^m}$, we present a design of a bit serial multiplier of Berlekamp type, which is very effective in computing $xy^2$. It is shown that our multiplier does not need a basis conversion process and a squaring operation is a simple permutation in our basis. Therefore our multiplier provides a fast and an efficient hardware architecture for a bit serial multiplication of two elements in ${\mathbb{F}}_{2^m}$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.430-432
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• 2015

This paper describes a hardware implementation of ultra-lightweight block cipher algorithm PRESENT-80/128 that supports for two master key lengths of 80-bit and 128-bit. The PRESENT algorithm that is based on SPN (substitution and permutation network) consists of 31 round transformations. A round processing block of 64-bit data-path is used to process 31 rounds iteratively, and circuits for encryption and decryption are designed to share hardware resources. The PRESENT-80/128 crypto-processor designed in Verilog-HDL was verified using Virtex5 XC5VSX-95T FPGA and test system. The estimated throughput is about 550 Mbps with 275 MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.485-487
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• 2017

The whirlpool hash function adopted as an ISO / IEC standard 10118-3 by the international standardization organization is an algorithm that provides message integrity based on an SPN (Substitution Permutation Network) structure similar to AES block cipher. In this paper, we describe the hardware implementation of the Whirlpool hash function. The round block is designed with a 64-bit data path and encryption is performed over 10 rounds. To minimize area, key expansion and encryption algorithms use the same hardware. The Whirlpool hash function was modeled using Verilog HDL, and simulation was performed with ModelSim to verify normal operation.

• Journal of the Chungcheong Mathematical Society
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• v.22 no.4
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• pp.789-797
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• 2009

Invertible transformations over n-bit words are essential ingredients in many cryptographic constructions. When n is large (e.g., n = 64) such invertible transformations are usually represented as a composition of simpler operations such as linear functions, S-P networks, Feistel structures and T-functions. Among them we will study T-functions which are probably invertible transformation and are very useful in stream ciphers. In this paper we will show that $f(x)=x+(g(x)^2{\vee}C)$ mod $2^n$ is a permutation with a single cycle of length $2^n$ if both the least significant bit and the third significant bit in the constant C are 1, where g(x) is a T-function.