• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.144-150
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• 1990

This paper describes radix-4 Fast Fourier Transform (FFT) Processor designed with the new twice perfect shuffle developed from a perfect shuffle used in radix-2 FFT algorithm. The FFT Processor consists of a butterfly arithmetic circuit, address generators for input, output and coefficient, input and output registers and controller. Also, it requires the external ROM for storage of coefficient and RAM for input and output. The butterfly circuit includes 12 bit-serial ($16{\times}8$) multipliers, adders, subtractors and delay shift registers. Operating on 25 MHz two phase clock, this processor can compute 256 point FFT in 6168 clocks, i.e. 247 us and provides flexibility by allowing the user to select any size among 4,16,64,and256points. Being fabricated with 2-um double metal CMOS process, it includes about 28000 transistors and 55 pads in $8.0{\times}8.2mm^2$area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.30-38
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• 2012

This paper presents packet detection, frequency offset estimation architecture and performance analysis for OFDM-based wireless personal area network (WPAN) systems. Packet detection structure is used to find the start point of a packet exactly in WPAN system as the correlation value passes the constant threshold value. The applied autocorrelation structure of the algorithm can be implemented simply compared to conventional packet detection algorithms. The proposed frequency offset estimation architecture is designed for phase rotation process structure, internal bit reduction to reduce hardware size and the frequency offset adjustment block to reduce look-up table size unlike the conventional structure. If the received signal can be compensated by estimated frequency offset through the correction block, it can reduce the impact on the frequency offset. Through the performance result, the proposed structure has lower hardware complexity and gate count compared to the conventional structure. Thus, the proposed structure for OFDM-based WPAN systems can be applied to the initial synchronization process and high-speed low-power WPAN chips.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.83-90
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• 2018

In this paper, we propose an algorithm for analyzing personal health log information in android environment, providing personal health log information in android environment, providing personalized exercise information and monitoring the condition of pedestrians. Personal health log data collection is performed based on raw data of user using MPU6050 sensor based on Arduino. Noise was removed and age threshold was applied to distinguish movement information. In addition, to protect personal information, safety is enhanced by providing anti-compilation prevention and encryption/decryption of APK file, and the result of movement information collection is measured according to sensor location. Experimental results showed that the MPU6050 sensor mounted one the ankle wsa measured 98.97% more accurately then the wrist. In addition, the loading time of SEED 128 bit encryption based DEX file has the average time of 0.55ms, minimizing the overhead.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.109-116
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• 2018

This paper describes an area-efficient design of SHA-256 hash function that is widely used in various security protocols including digital signature, authentication code, key generation. The SHA-256 hash processor includes a padder block for padding and parsing input message, so that it can operate without software for preprocessing. Round function was designed with a 16-bit data-path that processed 64 round computations in 128 clock cycles, resulting in an optimized area per throughput (APT) performance as well as small area implementation. The SHA-256 hash processor was verified by FPGA implementation using Virtex5 device, and it was estimated that the throughput was 337 Mbps at maximum clock frequency of 116 MHz. The synthesis for ASIC implementation using a $0.18-{\mu}m$ CMOS cell library shows that it has 13,251 gate equivalents (GEs) and it can operate up to 200 MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.438-449
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• 2012

This paper presents new CRC-p codes for VHF band maritime wireless communication system based on performance analysis of various CRC codes. For this purpose, we firstly describe the method of determination of undetected error probability and minimum Hamming distance according to variation of CRC codeword length. By using the fact that the dual code of cyclic Hamming code and primitive BCH code become maximum length codes, we present an algorithm for computation of undetected error probability and minimum Hamming distance where the concept of simple hardware that is consisted of linear feedback shift register is utilized to compute the weight distribution of CRC codes. We also present construction of transmit data frame of VHF band maritime wireless communication system and specification of major communication parameters. Finally, new optimal CRC-p codes are presented based on the simulation results of undetected error probability and minimum Hamming distance using the various generator polynomials of CRC codes, and their performances are evaluated with simulation results of bit error rate based on the Rician maritime channel model and ${\pi}$/4-DQPSK modulator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.379-385
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• 2003

In this paper, we propose a time constant control method for sieving local minimum problem of the multiuser detector using Hopfield neural network for synchronous multi-rate code division multiple access(CDMA) system in selective fading environments and its performance is compared with that of the parallel interference cancellation(PIC). We also assume that short scrambling codes of 256 chip length are used an uplink, suggest a simple correlation estimation algorithm and circuit complexity reduction method by using cyclostationarity property of short scrambling code.It is verified that multiuser detector using Hopfield neural network more efficiently cancels multiple access interference(MAI) and obtain better bit error rate and near-far resistant than conventional detector.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.10
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• pp.827-832
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• 2013

Holographic data storage system is affected by two dimensional intersymbol interference and inter-page interference. Especially, for multi-level holographic data storage system, since one pixel contains more than 1 bit, the system is more vulnerable to the error. In this paper, we propose a 2/3 modulation code for 4-level holographic data storage system. The proposed modulation code with error correcting capability could be compensated these interferences. Also, in this paper, we proposed a Viterbi decoder for 2/3 modulation code. The proposed Viterbi decoder eliminates unnecessary calculation. As a result, proposed 2/3 modulation code and Viterbi decoder has shown better performance than conventional one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.467-474
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• 1999

In this paper, Fault tolerant digital governor, using duplex I/O module and triplex CPU module and also 2 out of 3 voting algorithm and adding self diagnostic ability, is designed to realize ceaseless controlling and to improve the reliability of control system. The processor module of the system(SIDG-3000) is developed based on MC68EC040 32 Bit of Motorola, which guaranteed high quality of the module ,and SRAM for data also SRAM for command are separated. The process module also includes inter process communication function and power back up function (SRAM for back-up). System reliability is estimated by using the model of Markov process. The reliability of triplex system in mission time can be improved about 1.8 times in reliability 86%. 2.8 times in 95 %, 6 times in 99 % compared with a single control system. Designed digital governor system is applied after modelling of the steam turbine generator system of Buk-Cheju Thermal Power Plant. Simulation is carried out to prove the effectiveness of the designed digital governor system

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.643-650
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• 2014

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator adopts redundant binary number systems and a pipelined architecture to improve throughput and speed. It performs arctangent operation using vectoring mode of DCORDIC(Differential COordinate Rotation DIgital Computer) algorithm. Fixed-point MATLAB simulations are carried out to determine the optimal bit-widths and number of iteration. The phase calculator has ben verified by FPGA-in-the-loop verification using MATLAB/Simulink. A test chip has been fabricated using a TSMC $0.18-{\mu}m$ CMOS process, and test results show that the chip functions correctly. It has 82,000 gates and the estimated throughput is 400 MS/s at 400Mhz@1.8V.

• The KIPS Transactions:PartC
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• v.9C no.6
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• pp.847-856
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• 2002

Cellular network applications are growing drastically and this requires a fast and efficient transport method between the base station and the mobile switching center. One possible solution is to use ATM links. The low data rate and small-sized packets in the typical cellular applications imply that significant amount of link bandwidth would be wasted, if this small sized packet is carried by one ATM cell. For efficient operation for such cellular and low bit rate applications, a new type of ATM Adaptation Layer, AAL Type 2, has been proposed. In this paper, the principles of AAL Type 2 are briefly described along with the introduction of other alternatives which have formed the basis for this new AAL. The result from the simulation to study the performance of the AAL Type 2 is discussed from the view point of packet delay and ATM cell use efficiency. Due to the variable size of packets in this application, the fairness issue in serving variable sized packets is also discussed along with the effect of fair queueing algorithm implemented at AAL Type 2.