• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.6
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• pp.409-413
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• 2012

In this study, a substrate-bias assisted 2-step pulse programming method is proposed for realizing 4-bit/1-cell operation of the SONOS memory. The programming voltage and time are considerably reduced by this programming method than a gate-bias assisted 2-step pulse programming method and CHEI method. It is confirmed that the difference of 4-states in the threshold voltage is maintained to more than 0.5 V at least for 10-year for the multi-level characteristics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.10
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• pp.610-612
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• 2014

Mutilevel holographic data storage systems have a big advantage for capacity since it can store more than one bit per pixel. For instance, 2/3 modulation code stores 2/3(symbol/pixel) and 4/3(bit/pixel). Then it is about 1.3 bits per one pixel. In this paper, we propose two 4-level modulation codes, which have the minimum Euclidean distances of 3 and 4, respectively. The proposed codes perform better than random data. The performance of larger minimum distance code shows better than that of shorter one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.434-441
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• 2005

For LDPC decoding, received symbols are splitted bit by bit based using the received in-phase and quadrature components. The method of bit-splitting is affected on decoding performance because its method depend on distance over symbol constellation. Therefore this paper propose the bit split method using the sector information with sacrifice a little performance loss compared to Euclidean distance method. Futhermore DVB-S2 specification supports BC(Backward Compactible) mode which using the hierarchical modulation method, this paper also analyze the decoding performance according to deviation angle of 8PSK constellation for various LDPC coding rates.

• Journal of Korea Multimedia Society
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• v.8 no.2
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• pp.201-210
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• 2005

This paper proposes a power efficient 2-dimensional DCT/IDCT architecture driven by input data to be processed. The architecture achieves low power by taking advantage of the typically large fraction of zero and small-valued input processing data in video and image data compression. In particular, it skips multiplication by zero and dynamically activates/deactivates required bit-slices of fine-grain bit partitioned adders within multipliers and accumulators using simple input ANDing and bit-slice MASKing. The processed results from 1-D DCT/IDCT do not have unnecessary sign extension bits (SEBs), which are used for further power reduction in matrix transposer. The results extracted by bit-level transition activity simulations indicate significant power reduction compared to conventional designs.

• Journal of Internet of Things and Convergence
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• v.9 no.3
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• pp.81-86
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• 2023

SSD (solid state disk), which is flash memory-based storage device, has the advantages of high density and fast data processing. Therefore, it is being utilized as a storage device for high-capacity data storage systems that manage rapidly increasing big data. However, flash memory, a storage media, has a physical limitation that when the write/erase operation is repeated more than a certain number of times, the cells are worn out and can no longer be used. In this paper, we propose a method for converting defective multi-bit cells into single-bit cells to reduce the defect rate of flash memory and extend its lifetime. The proposed idea distinguishes the defects and treatment methods of multi-bit cells and single-bit cells, which have different physical characteristics but are treated as the same defect, and converts the expected defective multi-bit cells into single-bit cells to improve the defect rate and extend the overall lifetime. Finally, we demonstrate the effectiveness of our proposed idea by measuring the increased lifetime of SSD through simulations.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.226-229
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• 2000

In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.490-501
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• 1994

In this study the problems of cell marking method used in the field of ATM network traffic control are presented. Also an extended cell marking method considering the user level priority is proposed. The conventional traffic monitoring schemes set the CLP bit of a cell to 1 only under the circumstance of the violation of traffic contract. It causes that the number of low level cells increases and the levels of cells are lowered regardless of the user level priority. The three level priority control method combining FCI bit with CLP bit has also been proposed. It divides CLP=0 cells into two levels. Consequently, the proposed method preserves more cells in high level than the conventional one and the real loss of high level cells can be reduced. The performance of the proposed scheme has also been analyzed by the PBS(partial buffer sharing) with two thresholds for the proposed three levels. The result shows that the PBS with two thresholds can give more efficient control than the scheme with no priority, or the PBS with one threshold.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.125-136
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• 2009

This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.

• Journal of Communications and Networks
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• v.18 no.3
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• pp.333-339
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• 2016

A multi-stage turbo equalization scheme based on the bit-level combining (BLC) is proposed for multiple-input multiple-output (MIMO) systems with hybrid automatic repeat request (HARQ). In the proposed multi-stage turbo equalization scheme, the minimum mean-square-error equalizer at each iteration calculates the extrinsic log-likelihood ratios for the transmitted bits in a subpacket and the subpackets are sequentially replaced at each iteration according to the HARQ rounds of received subpackets. Therefore, a number of iterations are executed for different subpackets received at several HARQ rounds, and the transmitted bits received at the previous HARQ rounds as well as the current HARQ round can be estimated from the combined information up to the current HARQ round. In addition, the proposed multi-stage turbo equalization scheme has the same computational complexity as the conventional bit-level combining based turbo equalization scheme. Simulation results show that the proposed multi-stage turbo equalization scheme outperforms the conventional BLC based turbo equalization scheme for MIMO systems with HARQ.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.3
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• pp.197-205
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• 2004

In this paper, we studied on the hardware implementation of a 3${\times}$3 window weighted median filter using bit-level sorting algorithm. The weighted median filter is a generalization of the median filter that is able to preserve :,harp changes in signal and is very effective in removing impulse noise. It has been successfully applied in various areas such as digital signal and video/image processing. The weighted median filters are, for the most part, based on word-level sorting methods, which have more hardware and time complexity, However, the proposed bit-serial sorting algorithm uses weighted adder tree to overcome those disadvantages. It also offers a simple pipelined filter architecture that is highly regular with repeated modules and is very suitable for weighted median filtering. The algorithm was implemented by VHDL and graphical environment in MAX＋PlusII of ALTERA. The simulation results indicate that the proposed design method is more efficient than the traditional ones.