• Title/Summary/Keyword: Bit-Level

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A Two-bit Bus-Invert Coding Scheme With a Mid-level State Bus-Line for Low Power VLSI Design

  • Yoon, Myungchul
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.4
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    • pp.436-442
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    • 2014
  • A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.

Adaptive Bit-Reliability Mapping for LDPC-Coded High-Order Modulation Systems (LDPC 부호화 고차 변조 시스템을 위한 신뢰성 기반의 적응적 비트 매핑 기법)

  • Joo, Hyeong-Gun;Hong, Song-Nam;Shin, Dong-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.12C
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    • pp.1135-1141
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    • 2007
  • In this paper, an adaptive bit-reliability mapping is proposed for the bit-level Chase combining in LDPC-coded high-order modulation systems. Contrary to the previously known bit-reliability mapping that assigns the information (or parity) bits to more (or less) reliable bit positions, the proposed mapping adaptively assigns codeword bits to the bit positions of various reliabilities by considering the characteristics of code and protection levels of bits in high-order modulation symbol. Compared with the symbol-level Chase combining and the constellation rearrangement bit mapping, the proposed mapping gives $0.7{\sim}1.3$ dB and $0.1{\sim}1.0$ dB performance gain at $FER=10^{-3}$ with no additional complexity, respectively. Adaptive bit-reliability mappings are derived for various environments and the validity of them is confirmed through simulation.

A Study on PBS Mechanism with Two-Threshold in ATM Networks (ATM망에서 두 개의 임계값을 갖는 PBS 기법에 관한 연구)

  • 정현숙;신효영;박호균;류황빈
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.1
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    • pp.56-65
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    • 1994
  • As a method to control the congestion, priority mechanism which gives two-level priority to various traffics using CLP bit in cell haeder is carried in ATM network. In this paper, we proposed PBS(partial buffer sharing) mechanism with two threshold for provide three-level priority using CLP bit and Res. bit. By performance analysis proposed mechanism, we knew that provides flexibility to satisfy requirements of various quality of service, compare to existing mechanism with two-level priority.

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An Efficient Frame-Level Rate Control Algorithm for High Efficiency Video Coding

  • Lin, Yubei;Zhang, Xingming;Xiao, Jianen;Su, Shengkai
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.4
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    • pp.1877-1891
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    • 2016
  • In video coding, the goal of rate control (RC) is not only to avoid the undesirable fluctuation in bit allocation, but also to provide a good visual perception. In this paper, a novel frame-level rate control algorithm for High Efficiency Video Coding (HEVC) is proposed. Firstly a model that reveals the relationship between bit per pixel (bpp), the bitrate of the intra frame and the bitrate of the subsequent inter frames in a group of pictures (GOP) is established, based on which the target bitrate of the first intra frame is well estimated. Then a novel frame-level bit allocation algorithm is developed, which provides a robust bit balancing scheme between the intra frame and the inter frames in a GOP to achieve the visual quality smoothness throughout the whole sequence. Our experimental results show that when compared to the RC scheme for HEVC encoder HM-16.0, the proposed algorithm can produce reconstructed frames with more consistent objective video quality. In addition, the objective visual quality of the reconstructed frames can be improved with less bitrate.

A Study of Wavelet Image Coder for Minimizing Memory Usage (메모리 사용을 최소화하는 웨이블릿 영상 부호화기에 관한 연구)

  • 박성욱;박종욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.3C
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    • pp.286-295
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    • 2003
  • In this paper, the wavelet image coder, that can encode the image to various bit rate with minimum memory usage, is proposed. The proposed coder is used the 2D significant coefficient array(SCA) that has bit level informal on of the wavelet coefficients to reduce the memory requirement in coding process. The 2D SCA is two dimensional data structure that has bit level information of the wavelet coefficients. The proposed algorithm performs the coding of the significance coefficients and coding of bit level information of wavelet coefficients at a time by using the 2D SCA. Experimental results show a better or similar performance of the proposed method when compared with conventional embedded wavelet coding algorithm. Especially, the proposed algorithm performs stably without image distortion at various b it rates with minimum memory usage by using the 2D SCA.

Bit Depth Expansion using Error Distribution (에러 분포의 예측을 이용한 비트 심도 확장 기술)

  • Woo, Jihwan;Shim, Woosung
    • Journal of Broadcast Engineering
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    • v.22 no.1
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    • pp.42-50
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    • 2017
  • A Bit-depth expansion is a method to increase the number of bit. It is getting important as the needs of HDR (High Dynamic Range) display or resolution of display have been increased because the level of luminance or expressiveness of color is proportional to the number of bit in the display. In this paper, we present effective bit-depth expansion algorithm for conventional standard 8 bit-depth content to display in high bit-depth device (10 bits). Proposed method shows better result comparing with recently developed methods in quantitative (PSNR) with low complexity. The proposed method shows 1db higher in PSNR measurement with 40 times faster in computational time.

Image segmentation based on hierarchical structure and region merging using contrast for very low bit rate coding (초저속 부호화를 위한 계층적 구조와 대조를 이용한 영역 병합에 의한 영상 분할)

  • 송근원;김기석;박영식;이호영;하영호
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.34S no.11
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    • pp.102-113
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    • 1997
  • In this paepr, a new image segmentation method reducing efficiently contour information causing bottleneck problem at segmentatio-based very low bit rate codingis proposed, while preserving objective and subjective quality. It consists of 4-level hierarchical image segmentation based on mathematical morphology and 1-leve region merging structure using contast of two adjacent regions. For two adjacent region pairs at the fourth level included in each region of the thid level, contrast is calculated. Among the pairs of two adjacent regions with less value than threshold, two adjacent regions having the minimum contrast are merged first. After region merging, texture of the merged region is updated. The procedure is performed recursively for all the adjacent region pairs at the fourth level included in each region of the third level. Compared with the previous method, the objective and subjective image qualities are similar. But it reduces 46.65% texture information on the average by decreasing total region number to be tansmitted. Specially, it shows reduction of the 23.95% contour information of the average. Thus, it can improve efficiently the bottleneck problem at segementation-based very low bit rate coding.

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Improved FGS Coding System Based on Sign-bit Reduction in Embedded Bit-plane Coding

  • Seo, Kwang-Deok;Davies, Robert J.
    • IEMEK Journal of Embedded Systems and Applications
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    • v.2 no.3
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    • pp.129-137
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    • 2007
  • MPEG-4 FGS is one of scalable video coding schemes specified In ISO/IEC 14496-2 Amendment 2, and particularly standardized as a scheme for providing fine granular quality and temporal scalabilities. In this paper, we propose a sign-bit reduction technique in embedded bit-plane coding to enhance the coding efficiency of MPEG-4 FGS system. The general structure of the FGS system for the proposed scheme is based on the standard MPEG-4 FGS system. The proposed FGS enhancement-layer encoder takes as input the difference between the original DCT coefficient and the decision level of the quantizer instead of the difference between the original DCT coefficient and its reconstruction level. By this approach, the sign information of the enhancement-layer DCT coefficients can be the same as that of the base-layer ones at the same frequency index in DCT domain. Thus, overhead bits required for coding a lot of sign information of the enhancement-layer DCT coefficients in embedded bit-plane coding can be removed from the generated bitstream. It is shown by simulations that the proposed FGS coding system provides better coding performance, compared to the MPEG-4 FGS system in terms of compression efficiency.

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Improvements in Design and Evaluation of Built-In-Test System (무기체계 정비성 향상을 위한 BIT 설계 및 검증 방안)

  • Heo, Wan-Ok;Park, Eun-Shim;Yoon, Jung-Hwan
    • Journal of the Korea Institute of Military Science and Technology
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    • v.15 no.2
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    • pp.111-120
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    • 2012
  • Built-In-Test is a design feature in more and more advanced weapon system. During development test and evaluation(DT&E) it is critical that the BIT system be evaluated. The BIT system is an integral part of the weapon system and subsystem. Built-In-Test assists in conducting on system and subsystem failure detection and isolation to the Line Replaceable Unit(LRU). This capability reduces the need for highly skilled personnel and special test equipment at organizational level, and reduces maintenance down-time of system by shortening Total Corrective Maintenance Time. During DT&E of weapon system the objective of BIT system evaluation is to determine BIT capabilities achieved and to identify deficiencies in the BIT system. As a result corrective actions are implemented while the system is still in development. Through the use of the reiterative BIT evaluation the BIT system design was corrected, improved, or updated, as the BIT system matured.

Composition Rule of Character Codes to efficiently transmit the Character Code in HDLC(High-level Data Link Control) Protocol (HDLC(High-level Data Link Control) 프로토콜에서 효율적 문자부호 전송을 위한 문자부호화 규칙)

  • Hong, Wan-Pyo
    • The Journal of the Korea institute of electronic communication sciences
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    • v.7 no.4
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    • pp.753-760
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    • 2012
  • This paper is to show the character coding rule in computer and information equipment etc to improve the transmission efficiency in telecommunications. In the transmission system, the transmission efficiency can be increased by applying the proper character coding method. In datalink layer, HDSL ptotocol use FLAG byte to identify the frame to frame which consists of data bit stream and other control bytes. FLAG byte constits of "01111110". When data bit stream consist of the consecutive 5-bit "1" after "0", the decoder can not distinguish whether the data bit sequence is flag bit stream or data bit stream. To solve the problem, when the line coder in transmitter detects the consecutive 5-bits "1" after "0" in the input data stream, inserts violently the "0" after 5th "1" of the consecutive 5-bit "1" after "0". As a result, when the characters are decoded with the above procedure, the efficiency of system should be decreased. This paper shows the character code rule to minimize the consecutive 5-bits "1" after "0" when the code is given to each characters.