• Journal of Korea Multimedia Society
• /
• v.21 no.3
• /
• pp.415-422
• /
• 2018

Advances of telecommunication technology bring various changes in journalism field. Reporters started to gather, edit, and transmit content to main server in media company using hand-held smart media and notebook computer. This paper tried to testify valid bit-rate of visual news content using LTE network and mobile phone. Field news like natural disasters need real-time transmission of video content. But broadcasting company normally use heavy ENG system and transmission satellite trucks. We prepared and experimented different types of visual content that has different bit-rates. Transmission tool was LU-60HD mobile system of LiveU Corporation. Transmission result shows that bit-rate of 2Mbps news content is not suitable for broadcasting and VBR (Variable Bit Rate) transmission has better definition quality than CBR (Constant Bit Rate) method. Three different bit-rate of VBR transmission result shows that 5Mbps clip has better quality than 1Mbps and 3Mbps. The higher bit-rate, the better video quality. But if the content has much movements, that cause delay and abnormal quality of video. So optimizing the balance between stability of signal and quality of bit-rate is crucial factor of real-time broadcasting news gathering business.

• Journal of Korea Society of Industrial Information Systems
• /
• v.20 no.1
• /
• pp.1-7
• /
• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.15 no.2
• /
• pp.111-120
• /
• 2012

Built-In-Test is a design feature in more and more advanced weapon system. During development test and evaluation(DT&E) it is critical that the BIT system be evaluated. The BIT system is an integral part of the weapon system and subsystem. Built-In-Test assists in conducting on system and subsystem failure detection and isolation to the Line Replaceable Unit(LRU). This capability reduces the need for highly skilled personnel and special test equipment at organizational level, and reduces maintenance down-time of system by shortening Total Corrective Maintenance Time. During DT&E of weapon system the objective of BIT system evaluation is to determine BIT capabilities achieved and to identify deficiencies in the BIT system. As a result corrective actions are implemented while the system is still in development. Through the use of the reiterative BIT evaluation the BIT system design was corrected, improved, or updated, as the BIT system matured.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.4
• /
• pp.1-9
• /
• 2002

The distribution characteristics of data retention time for DRAM was studied in connection with the probability distribution of the cell parameters. Using the cell parameters and the transient characteristics of cell node voltage, data retention time was investigated. The activation energy for dielectric layer growth on cell capacitance, the recombination trap energy for leakage current in the junction depletion region, and the sensitivity characteristics of sense amplifier were used as the random variables to perform the Monte Carlo simulation, and the probability distributions of cell parameters and distribution characteristics of cumulative failure bit on data retention time in DRAM cells were calculated. we found that the sensitivity characteristics of sense amplifier strongly affected on the tail bit distribution of data retention time.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3067-3069
• /
• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• Journal of the Korea Society of Computer and Information
• /
• v.24 no.11
• /
• pp.21-27
• /
• 2019

Recently, embedded systems have been introduced in various fields such as smart factories, industrial drones, and medical robots. Since sensor data collection and IoT functions for machine learning and big data processing are essential in embedded systems, it is essential to port the operating system that is suitable for the function requirements. However, in embedded systems, it is necessary to separate the hard real-time system, which must process within a fixed time according to service characteristics, and the flexible real-time system, which is more flexible in processing time. It is difficult to port the operating system to a low-performance embedded device such as 8BIT MCU to perform simultaneous real-time. When porting a real-time OS (RTOS) to a low-specification MCU and performing a number of tasks, the performance of the real-time and general processing greatly deteriorates, causing a problem of re-designing the hardware and software if a hard real-time system is required for an operating system ported to a low-performance MCU such as an 8BIT MCU. Research on the technology that can process real-time processing system requirements on RTOS (ported in low-performance MCU) is needed.

• Journal of the Korean Society of Fisheries and Ocean Technology
• /
• v.22 no.1
• /
• pp.34-40
• /
• 1986

This paper deals with a new bit conversion method. When 12 bit AID converter is adapted to 16 bit micro-computer, complicated data aquisition method is not necessary to acquire the AID converted data into memory of computer. However, when the 12 bit AID converter is adapted to the 8 bit micro-computer 12 bit data should be divided into 4 bit data and 8 bit data. Therefore the old data-dividing method made 4 bitl2byte of memory space wasted. On the contrary, using the new bit conversion method suggested in this paper the two of 12 bit data are converted into 3 byte of data without extending the AID conversion time.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.8A
• /
• pp.942-949
• /
• 2004

This paper proposes and analyzes the anti-collision algorithm in Ubiquitous ID system. We mathematically compares the performance of the proposed algorithm with that of binary search algorithm, slotted binary tree algorithm using time slot, and bit-by-bit binary tree algorithm proposed by Auto-ID center. We also validated analytic results using OPNET simulation. Based on the analytic results, comparing the proposed algorithm with bit-by-bit algorithm which is the best of existing algorithms, the performance of proposed algorithm is about 5% higher when the number of tags is 20, and 100% higher when the number of tags is 200.

• ETRI Journal
• /
• v.45 no.4
• /
• pp.615-626
• /
• 2023

Under limited transmission conditions, many factors affect the efficiency of video transmission. During the flight of an unmanned aerial vehicle (UAV), frequent network switching often occurs, and the channel transmission condition changes rapidly, resulting in low-video transmission efficiency. This paper presents an efficient video coding flow for UAVs working in the 5G nonstandalone network and proposes two bit controllers, including time and spatial bit controllers, in the flow. When the environment fluctuates significantly, the time bit controller adjusts the depth of the recursive codec to reduce the error propagation caused by excessive network inference. The spatial bit controller combines the spatial bit mask with the channel quality multiplier to adjust the bit allocation in space to allocate resources better and improve the efficiency of information carrying. In the spatial bit controller, a flexible mini graph is proposed to compute the channel quality multiplier. In this study, two bit controllers with end-to-end codec were combined, thereby constructing an efficient video coding flow. Many experiments have been performed in various environments. Concerning the multi-scale structural similarity index and peak signal-to-noise ratio, the performance of the coding flow is close to that of H.265 in the low bits per pixel area. With an increase in bits per pixel, the saturation bottleneck of the coding flow is at the same level as that of H.264.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.1
• /
• pp.67-74
• /
• 2000

In this paper, a $54{\times}54$-bit multiplier based on a improved conditional sum adder is proposed. To reduce the multiplication time, high compression-rate compressors without Booth's Encoding, and a 108-bit conditional sum adder with separated carry generation block, are developed. Furthermore, a design technique based on pass-transistor logic is utilized for optimize the multiplication time and the power consumption by about 5% compared to that of conventional one. With $0.65{\mu}m$, single-poly, triple-metal CMOS process, its chip size is $6.60{\times}6.69\;mm^2$ and the multiplication time is 135.ns at a 3.3V power supply.