• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.197-212
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• 1990

This paper present a new design concept of a single chip 16-bit data path using the concept of modular design, the whole system is divided into several blocks which can be operated as an independent system itself. Making the internal blocks can act as a subsystem, it is possible to shorten design turn-around time, to be redesigned effectively, and to optimize the system performance. The designed system is data path. The data path is to manipulate 16-bit integer data. It is composed of aritmetic logic unit, register file, barrel shifter and bus circuit. The widths and lengths of gate in the circuit were determined using SPICE2. The results of circuit simulation were in good agreement with expected circuit characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.9-14
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• 2009

In this paper, we proposed a novel OTP unit bit of CMOS gate oxide antifuse using the standard CMOS process without additional process. The proposed OTP unit bit is composed of 3 transistors including an NMOS gate oxide antifuse and a sense amplifier of inverter type. The layout area of the proposed OTP unit bit is $22{\mu}m^2$ similar to a conventional OTP unit bit. The programming time of the proposed OTP unit bit is 3.6msec that is improved than that of the conventional OTP unit bit because it doesn't use high voltage blocking elements such as high voltage blocking switch transistor and resistor. And the OTP array with the proposed OTP unit bit doesn't need sense amplifier and bias generation circuit that are used in a conventional OTP array because sense amplifier of inverter type is included to the proposed OTP unit bit.

• Explosives and Blasting
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• v.38 no.1
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• pp.14-22
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• 2020

Bit damage is one of the primary causes of decreasing drilling efficacy. Nevertheless the management of bit ware and failure are often left for field engineers' experience. Thus it is imperative to establish a proper system to predict and manage the bit damage during the rock drilling process. In this study, the drilling sound signal has been recorded and analyzed using wavelet transform analysis to identify the exact moment of bit failure. Through the analysis wavelet time-frequency spectrums have been constructed and an abnormal point has been identified with 0.9 of wavelet transform value at the 652.8s on a frequency band around 500Hz. Furthermore it is also observed that the penetration rate of the damaged bit has been decreased to 23mm/s which is 9mm/sec lower than the average of undamaged bit. The study verifies that wavelet transform analysis can be used to build a system to diagnose the bit damage while drilling.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.56-63
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• 2008

This paper describes a 12 bit 1GS/s current mode segmented DAC for WCDMA communication. The proposed circuit in this paper employes segmented structure which consists of 4bit binary weighted structure in the LSB and 4bit thermometer decoder structure in the mSB and MSB. The proposed DAC uses delay time compensation circuits in order to suppress performance decline by delay time in segmented structure. The delay time compensation circuit comprises of phase frequency detector, charge pump, and control circuits, so that suppress delay time by binary weighted structure and thermometer decoder structure. The proposed DAC uses CMOS $0.18{\mu}m$ 1-poly 6-metal n-well process, and measured INL/DNL are below ${\pm}0.93LSB/{\pm}0.62LSB$. SFDR is approximately 60dB and SNDR is 51dB at 1MHz input frequency. Single DAC's power consumption is 46.2mW.

• Journal of Digital Contents Society
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• v.16 no.5
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• pp.775-781
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• 2015

EBS started 2HD MMS experimental broadcasting for the first time in Korea on Feb. 11, 2015. It uses the picture compression technique based on MPEG-2 CODEC, and applies the result of the experiment about variable bit rates and changes according to the scanning types, 1080i and 720p. But when changing channels, the delay in displaying picture occurs because of the operation of the variable GOP on MMS broadcasting, which optimizes image quality by application variable bit rates. In this study, verified the relationship between the decoding time of I frames and the GOP set in the encoding step by experimenting and analyzing ON-AIR TS. By using the verification data and adjusts the Encoder GOP parameters, improved the different video display time delays according to the scanning mode 1080i and 720p.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.11
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• pp.924-927
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• 2017

This paper presents a 6~18 GHz 8-bit true time delay (TTD) circuit. The unit delay circuit is based on m-derived filter with relatively constant group delay. The designed 8-bit TTD is implemented with two single-pole double-throw (SPDT) switches and seven double- pole double-throw (DPDT) switches. The reflection characteristics are improved by using inductors. The designed 8-bit TTD was fabricated using $0.18{\mu}m$ CMOS. The measured delay control range was 250 ps with 1 ps of delay resolution. The measured RMS group delay error was less than 11 ps at 6~18 GHz. The measured input/output return losses are better than 10 dB. The chip consumes zero power at 1.8 V supply. The chip size is $2.36{\times}1.04mm^2$.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.2
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• pp.49-61
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• 2009

Finite Field multiplication operation is one of the most important operations in the finite field arithmetic. Recently, Fan and Dai introduced a Shifted Polynomial Basis(SPB) and construct a non-pipeline bit-parallel multiplier for $F_{2^n}$. In this paper, we propose a new bit-parallel shifted polynomial basis type I and type II multipliers for $F_{2^n}$ defined by an irreducible trinomial $x^{n}+x^{k}+1$. The proposed type I multiplier has more efficient the space and time complexity than the previous ones. And, proposed type II multiplier have a smaller space complexity than all previously SPB multiplier(include our type I multiplier). However, the time complexity of proposed type II is increased by 1 XOR time-delay in the worst case.

• International Journal of Precision Engineering and Manufacturing
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• v.4 no.1
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• pp.9-14
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• 2003

In this study we suggest real-time simulator that could describe rent system without ordinary DSP card. This simulator is composed of 80196kc-16bit ordinary microprocessor, which is widely used up to now and personal computer. DSP card that has calculated complex numerical equation is replaced by personal computer and 80196kc generates control signals independently out of the personal computer. In all process personal computer is synchronized with one-board microprocessor (80196kc) within sampling time in the closed loop system. This makes it possible to be described in hydraulic servo system in real time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2401-2408
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• 1997

The measured pulse shapes provided in the given data package demonstrated pulse distortions due to laser speckle. the distorted pulse shapes were carefully analyzed, modeled, and then applied to the DTTL(Digital-data Transition Tracking Loop)[1] bit synchronizer simulator to measure the mean time delay and its delay variation performance. The result showed that the maximum mean time delay variation with the modeled data was 12.5% when window size equals 1. All the data given were located within this modeled boundary and the maximum eman time delay variation was 7% in this case. The mean time delay variation was known to be smaller by reducing the window size [2][5][6]. The mitigated delay variation was 2.5% in the modeled case and 1.4% in the data set given when the windown size equals 0.1. With the digital DTTL insteal of analog DTTL, similar results was obtained.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1131-1134
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• 1999

In general CELP type vocoders provide good speech quality around 4.8kbps. Among them, G.723.1 developed for Internet Phone and videoconferencing includes two vocoders, 5.3kbps ACELP and 6.3kbps MO-MLQ. Since 6.3kbps MP-MLQ requires large amount of computation for fixed codebook search, it is difficult to realize real time processing. In order to improve the problem this paper proposes the new method that reduces the processing time up to about 50% of codebook search time. We first decide the grid bit, then search the codebook. Grid bit is selected by comparison between synthetic speech, which is synthesized with only odd or even pulses of target vector. and DC removed original speech. As a result, we reduced the total processing time of G.723.1 MP-MLQ up to about 26.08%. In objective quality test 11.19㏈ of segSNR was obtained, and in subjective quality test there was almost no speech degradation.