• The KIPS Transactions:PartB
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• v.9B no.1
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• pp.77-82
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• 2002

Progressive image transmission involves a progressive increase in the image resolution at the receiver from a lower to a higher resolution during the transmission of data. This is an effective way of using a limited transmission channel, because, after estimating the value of the data in the early transmission period, a decision can be made whether or not to proceed with the transmission of the remaining part. To realize more effective progressive image transmission, the current thesis divides an image into bit planes and then re-organizes each plane into a complementary quadtree structure. As a result, by transmitting the data on each bit plane and each level of the complementary quadtree in the appropriate order, the basic image contents can be understood with less data in the early period of transmission.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2267-2270
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• 2003

This paper has been studied to implement MQ encoder in JPEG2000 on FPGA. In the JPEG2000 architecture, Each of coding passes collects contextual information about the bit-plane data. An MQ coder uses contextual information and its internal state to decode a compressed bit-stream. This paper draws up JPEG2000 Standard Part 1: FCD 15444-1 It is simulated with Modelsim and tested with JBIG2 data.

• Korean Journal of Remote Sensing
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• v.8 no.1
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• pp.59-69
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• 1992

The IMAPRO sotfware package was mainly focused to provide an algorithm which is capable of displaying various color composite images on IBM PC, VGA(Video Graphic Array) card with no special hardware. It displays the false color images using a low-cost eight-bit place refresh buffer. This produces similar quality to the one obtained from image board with three eight-bit plane. Also, it provides user friendly menu driven method for the user who are not familier with technical knowladge of image processing. It may prove useful for universities, institute and private company where expensive hardware is not available.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.160-172
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• 2014

Although Wyner-Ziv (WZ) video coding proves useful for applications employing encoders having restricted computing resources, the WZ decoder has a problem of excessive decoding complexity. It is mainly due to its iterative LDPC channel decoding process which repeatedly requests incremental parity data after iterative channel decoding of parity data received at each request. In order to solve the complexity problem, we divide bit planes into two groups and estimate the minimum required number of parity requests separately for the two groups of bit planes using bit plane correlation. The WZ decoder executes the iterative decoding process only after receiving parity data corresponding to the estimated minimum number of parity requests. The proposed method saves about 71% of the computing time in the LDPC decoding process.

• Proceedings of the Korea Contents Association Conference
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• 2006.11a
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• pp.250-253
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• 2006

In this paper, we proposed a new method of the Adaptive steganography using complexity on bit planes of color image. Applying fixing threshold and variable length, if insert information into all bit plans, all bit plans showed different image quality. Therefore, we first defined the complexity on bit plane and data complexity, similarity insert information into bit plans. As a result, the proposed method increased the insertion capacity and improved the image quality than fixing threshold and variable length method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.2
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• pp.36-43
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• 1985

This paper describes a DRC (Design Rule Check) algorithm and its program implement-ation which requires CPU time linearly proportional to the number of rectangular patterns n the NMOS If layout. While the CPU time for conventional DRC algorithm is proportion-al to 0(nlogn) or 0(n**1.2), (n:number of rectangles it was shown that the present also-rithm only consumes CPU time linearly proportional to 0(n).

• Journal of Astronomy and Space Sciences
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• v.23 no.1
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• pp.19-28
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• 2006

The noise temperature of existing millimeter-wave receivers is already within two or three times quantum noise limit. One of practical ways to increase the observation speed of single dish radio telescope without longer integration time is use of multi-beam focal plane array receiver as demonstrated in several large single dish radio telescopes. In this context the TRAO (Taeduk Radio Astronomy Observatory), which operates a 143n Cassegrain radio telescope, is planning to develop a 4 x 4 beams focal plane array SIS receiver system for 86-115 GHz band. Even though millimeter-wave HEMT LNA-based receivers approach the noise temperature comparable to the SIS receiver at W-band, it is believed that the receiver based on SIS mixer seems to offer a bit more advantages. The critical part of the multi-beam array receiver will be sideband separating SIS mixers. Employing such a type of SIS mixer makes it possible to simplify the quasi-optics of receiver. Otherwise, an SSB filter should be used in front of the mixer or some sophisticated post-processing of observation data is needed. In this paper we will present a preliminary design concept and components needed for the development of a new 3 mm band multi-beam focal plane array receiver.

• Journal of Magnetics
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• v.16 no.4
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• pp.328-331
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• 2011

Here, we describe a dual spin valve structure with distinct switching fields for two pinned layers. A device with this structure has a staircase of three distinct magnetoresistive states. The multiple resistance states are achieved by controlling the exchange coupling between two ferromagnetic pinned layers and two adjacent anti-ferromagnetic pinning layers. The maximum magnetoresistance ratio is 7.9% for the current-perpendicular-to-plane and 7.2% for the current-in-plane geometries, with intermediate magnetoresistance ratios of 3.9% and 3.3%, respectively. The requirements for using this exchange-biased stack as a three-state memory device are also discussed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.57-62
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• 2011

In this paper, an efficient architecture for MFVLD(Multi-Format Variable Length Decoder) which can process H.264, MPEG-2, MPEG-4, AVS, VC-1 bitstream is proposed. The proposed MF-VLD is designed to be adapted to the MPSOC (Multi-processor System on Chip) architecture, uses bit-plane algorithm for the processing of inverse quantized data to reduce the width of AHB bus. External SDRAM is used to minimize the internal memory size. In this architecture, the adding or removing each variable length decoder can be easily done by using multiplexor. The designed MF-VLD can be operated in 200MHz at 0.18um process. The gate size is 657K gate and internal memory size is 27Kbyte.

• Journal of Broadcast Engineering
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• v.13 no.3
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• pp.289-298
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• 2008

We propose an SNR-scalable coding algorithm for three-dimensional mesh sequences based on singular value decomposition (SVD). SVD achieves a coding gain by representing a mesh sequence with a small number of basis vectors and singular values. First, we introduce a bit plane coding scheme and derive a quantitative relationship between each bit plane and the reconstructed image quality. Using the relationship, we develop a rate-distortion (RD) optimized coding algorithm. Moreover, we propose prediction techniques to exploit the spatio-temporal correlations in real mesh sequences. Simulation results demonstrate that the proposed algorithm provides significantly better RD performance than conventional SVD coders.