• Title/Summary/Keyword: Bit error

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Performance Analysis of IEEE 802.11b under IEEE 802.15.4 Environment (IEEE 802.15.4 환경 하에서의 IEEE 802.11b의 성능 해석)

  • Yoon, Dae-Kil;Shin, Soo-Young;Kwon, Wook-Hyun;Kim, Jung-Jun;Kim, Young-Ho;Shin, Young-Hee
    • Journal of The Institute of Information and Telecommunication Facilities Engineering
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    • v.4 no.2
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    • pp.9-17
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    • 2005
  • Coexistence of different wireless systems that share the 2.4 GHz ISM frequency band is becoming one of the most important issue. This paper presents a model of the interference that IEEE 802.11b affected by IEEE 802.15.4. The packet error rate (PER) of IEEE 802.11b under the interference of IEEE 802.15.4 is analyzed. The PER is obtained by using the bit error rate (BER) and the collision time. Further, this paper suggests a packet length to reduce the effect of the IEEE 802.15.4 interference and obtain a maximum throughput of the IEEE 802.11b. The analytical results are validated using simulation.

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Generation of Error corrector for Holographic Data Storage system Used The Extended Kalman filter (확장 칼만필터를 이용한 홀로그래픽 에러 보정 알고리즘)

  • Kim Janghyun;Yang Hyunseok;Park Jinbae;Park Youngpil
    • 정보저장시스템학회:학술대회논문집
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    • 2005.10a
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    • pp.44-46
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    • 2005
  • Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part therefore fast data transfer rate and high storage capacity about $1Tb/cm^3$ can be realized. In this paper, to reduce errors of binary data stored in holographic data storage system, a new method for bit error reduction is suggested. We proposal Algorithm use The Extended Kalman filter. The Kalman filter reduce measurement noise. Therefore, By using this error reduction method following results are obtained; the effect of measurement nois of Pixel is decreased and the intensity profile of data page becomes uniform therefore the better data storage system can be constructed.

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Design error corrector of binary data in holographic dnta storage system using fuzzy rules (근접 픽셀 에러 감소를 위한 홀로그래픽 데이터 스토리지 시스템의 퍼지 규칙 생성)

  • Kim Jang-hyun;Kim Sang-hoon;Yang Hyun-seok;Park Jin-bae;Park Young-Pil
    • 정보저장시스템학회:학술대회논문집
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    • 2005.10a
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    • pp.129-133
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    • 2005
  • Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part therefore fast data transfer rate and high storage capacity about $1Tb/cm^3$ can be realized. In this paper, to reduce errors of binary data stored in holographic data storage system, a new method for bit error reduction is suggested. First, find cluster centers using subtractive clustering algorithm then reduce intensities of pixels around cluster centers and fuzzy rules. Therefore, By using this error reduction method following results are obtained ; the effect of Inter Pixel Interference noise is decreased and the intensity profile of data page becomes uniform therefore the better data storage system can be constructed.

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Performance and Energy Consumption Analysis of 802.11 with FEC Codes over Wireless Sensor Networks

  • Ahn, Jong-Suk;Yoon, Jong-Hyuk;Lee, Kang-Woo
    • Journal of Communications and Networks
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    • v.9 no.3
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    • pp.265-273
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    • 2007
  • This paper expands an analytical performance model of 802.11 to accurately estimate throughput and energy demand of 802.11-based wireless sensor network (WSN) when sensor nodes employ Reed-Solomon (RS) codes, one of block forward error correction (FEC) techniques. This model evaluates these two metrics as a function of the channel bit error rate (BER) and the RS symbol size. Since the basic recovery unit of RS codes is a symbol not a bit, the symbol size affects the WSN performance even if each packet carries the same amount of FEC check bits. The larger size is more effective to recover long-lasting error bursts although it increases the computational complexity of encoding and decoding RS codes. For applying the extended model to WSNs, this paper collects traffic traces from a WSN consisting of two TIP50CM sensor nodes and measures its energy consumption for processing RS codes. Based on traces, it approximates WSN channels with Gilbert models. The computational analyses confirm that the adoption of RS codes in 802.11 significantly improves its throughput and energy efficiency of WSNs with a high BER. They also predict that the choice of an appropriate RS symbol size causes a lot of difference in throughput and power waste over short-term durations while the symbol size rarely affects the long-term average of these metrics.

R-S Decoder Design for Single Error Correction and Erasure Generation (단일오류 정정 및 Erasure 발생을 위한 R-S 복호기 설계)

  • Kim, Yong Serk;Song, Dong Il;Kim, Young Woong;Lee, Kuen Young
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.5
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    • pp.719-725
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    • 1986
  • Reed-solomon(R-S) code is very effective to coerrect both random and burst errors over a noise communication channel. However, the required hardware is very complex if the B/M algorithm was employed. Moreover, when the error correction system consists of two R-S decoder and de-interleave, the I/O data bns lines becomes 9bits because of an erasure flag bit. Thus, it increases the complexity of hardware. This paper describes the R-S decoder which consisits of a error correction section that uses a direct decoding algorithm and erasure generation section and a erasure generation section which does not use the erasure flag bit. It can be shown that the proposed R-S dicoder is very effective in reducing the size of required hardware for error correction.

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A Study on High Precision and High Stability Digital Magnet Power Supply Using Second Order Delta-Sigma modulation (2차 델타 시그마 변조기법을 이용한 고 정밀 및 고 안정 디지털 전자석 전원 장치에 관한 연구)

  • Kim, Kum-Su;Jang, Kil-Jin;Kim, Dong-Hee
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.29 no.3
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    • pp.69-80
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    • 2015
  • This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.

Design and Fabrication of 5-Bit Broadband MMIC Phase Shifter (5-Bit 광대역 MMIC 위상 변위기 설계 및 제작)

  • 정상화;백승원;이상원;정기웅;정명득;우병일;소준호;임중수;박동철
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.2
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    • pp.123-129
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    • 2002
  • 5-bit broadband MMIC phase shifter has been designed and fabricated. For the broadband performance, 11.25$^{\circ}$, 22.5$^{\circ}$, 45$^{\circ}$ and 90$^{\circ}$ bit have been designed with Lange coupler and 180$^{\circ}$ bit has been implemented by using shorted coupled line with Lange coupler and $\pi$-network of transmission line. Due to Lange coupler with large size, the Lange couplers have been folded far circuit size reduction. Low loss PIN diode has been utilized as a switch for each bit. Fabricated 5-bit broadband phase shifter shows the measured results that RMS phase error of 5 major phases is 3.5$^{\circ}$, maximum insertion loss is 12.5 dB, and maximum input and output return loss are 7 dB and 10 dB, respectively. The size of fabricated phase shifter is 6.5$\times$5.3 $ extrm{mm}^2$.

Generalized BER Performance Analysis for Uniform M-PSK with I/Q Phase Unbalance (I/Q 위상 불균형을 고려한 Uniform M-PSK의 일반화된 BER 성능 분석)

  • Lee Jae-Yoon;Yoon Dong-Weon;Hyun Kwang-Min;Park Sang-Kyu
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.3C
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    • pp.237-244
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    • 2006
  • I/Q phase unbalance caused by non-ideal circuit components is inevitable physical phenomenons and leads to performance degradation when we implement a practical coherent M-ary phase shift keying(M-PSK) demodulator. In this paper, we present an exact and general expression involving two-dimensional Gaussian Q-functions for the bit error rate(BER) of uniform M-PSK with I/Q phase unbalance over an additive white Gaussian noise(AWGN) channel. First we derive a BER expression for the k-th bit of 8, 16-PSK signal constellations when Gray code bit mapping is employed. Then, from the derived k-th bit BER expression, we present the exact and general average BER expression for M-PSK with I/Q phase unbalance. This result can readily be applied to numerical evaluation for various cases of practical interest in an I/Q unbalanced M-PSK system, because the one- and two-dimensional Gaussian Q-functions can be easily and directly computed using commonly available mathematical software tools.

A Performance of Complementary Code Keying Codes

  • Lee Yu Sung;Park Hyun Cheol
    • Proceedings of the IEEK Conference
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    • 2004.08c
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    • pp.645-648
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    • 2004
  • In this paper, we drive a theoretical performance of complementary code keying (CCK) codes on additive white Gaussian noise (AWGN) channel. The CCK codes can be demodulated by the optimal maximum likelihood decoding method and sub-optimal correlation magnitude decoding algorithm. We calculate the bit error rate (BER) and symbol or codeword error rate (SER) of the CCK codes using the above mentioned two decoding algorithms. To derive the error performance, we use the weigh distributions and cross-correlation distributions of CCK codes.

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The Error Rate Evaluation for Differential Demodulation of 2-h Continuous Phase Modulation (차동 복조 2-h 연속 위성 변조의 오류 확률)

  • 윤동원;한영열
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.7
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    • pp.29-35
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    • 1994
  • The performance of continuous phase modulation signals is well known for the coherent demodulation. But the carrier recovery circuits of the coherent receiver have long acquisition time and the receiver experiences high error floors for fading channels. In this paper, we propose the differential demodulation of 2-h continuous phase modulation signals. The sets of modulation indices of 2-h phase codes adequate to the differential demodulation for differentially encoded input are obtained and the average bit error probability in Additive White Gaussian Noise environments is derived and analyzed.

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