• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.210-216
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• 2000

The features of bit error rate (BER) are discussed, how to analyze statistics of the bit error rate. How many will the BER be improved after correcting one single-error in the block\ulcorner The answer is satisfactory in this paper.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.57-62
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• 2011

This paper presents a study on the performance analysis on probability of bit error for wavelet in 4-ary SWSK system. The formula for the bit error probability in 4-ary SWSK system was derived from the conventional method. This paper experimentally implements the probability of bit error for Daubechies, Biorthogonal, Coiflet and Symlet wavelet using the conventional formula of bit error probability. Additionally, the performance of bit error probability is analyzed for the period and the number of wavelet taps. Based on the results, we confirmed that the performance of Coiflet and Symlet wavelet for the probability of bit error is superior to the other wavelet, and their probability of bit error are similar.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1997.11a
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• pp.137-146
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• 1997

The simplest bit error detection scheme is to append a parity bit to the end of a bit sequence. In this paper an error correction technique with the use of a parity bit is proposed, and the performance of the proposed system is analyzed. The error probability of the proposed system is compared with the output of computer simulation of the proposed system. It is also compared with the error probability of error at BPSK system, and the signal-to-noise ratio gain is showed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.445-454
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• 2015

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10A
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• pp.958-964
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• 2007

In this paper, we derive the relationship between the bit error probability (BEP) of maximum a posteriori (MAP) bit detection and the bit minimum mean square error (MMSE), that is, the BEP is greater than a quarter of the bit USE and less than a half of the bit MMSE. By using this result, the lower and upper bounds of the derivative of the mutual information are derived from the BEP and the lower and upper bounds are easily obtained in the multiple-input multiple-output (MIMO) communication systems with the bit-linear linear-dispersion (BLLD) codes in the Gaussian channel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• Progress in Superconductivity
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• v.7 no.1
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• pp.36-40
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• 2005

The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been a very important issue. In this work, we calculated the bit error rate of an RSFQ switch used in superconductive arithmetic logic unit (ALU). RSFQ switch should have a very low error rate in the optimal bias. Theoretical estimates of the RSFQ error rate are on the order of $10^{-50}$ per bit operation. In this experiment, we prepared two identical circuits placed in parallel. Each circuit was composed of 10 Josephson transmission lines (JTLs) connected in series with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to both circuits. The outputs of the two circuits were compared with an RSFQ exclusive OR (XOR) to measure the bit error rate of the RSFQ switch. By using a computerized bit-error-rate test setup, we measured the bit error rate of $2.18{\times}10^{-12}$ when the bias to the RSFQ switch was 0.398 mA that was quite off from the optimum bias of 0.6 mA.

• The Journal of the Korea Contents Association
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• v.8 no.10
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• pp.37-44
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• 2008

This paper presented a solution to encryption and decryption problem suffering data transmission error for encrypted message transmission. Block cypher algorithms experience avalanche effect that a single bit error in an encrypted message brings substantial error bits after decryption. The proposed fault tolerant scheme addresses this error avalanche effect exploiting a multi-dimensional data array shuffling process and an error correction code. The shuffling process is to simplify the error correction. The shuffling disperses error bits to many data arrays so that each n-bit data block may comprises only one error bit. Thereby, the error correction scheme can easily restore the one bit error in an n-bit data block. This scheme can be extended on larger data blocks.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.97-105
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• 1994

Transform image coding using DCT is proved to be efficient in the absence of channel error but its performance degrades rapidly over noisy channel. In this paper, in the case of appling bit selcetive error correction coding that protects some significant bits in a codeword, an efficient allocation method of imformation bits and additive redundancy bits used for quantization and error correction coding respectively under constant transmission bit rate is proposed, and its performance is analyzed. As a result, without increasing trasmission bit rate, PSNR can be improved up to 7~8 [dB] below bit error rate $10^2$ and the image without blocking effect caused by bit error resulted from channel noise can be recostructed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.19-26
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• 1993

The bit error probability of Reed-Solomon/convolutional concatenated codes can be more exactly calculated by using a more approximate bound of the symbol error probability of the convolutional codes. This paper obtains the unequal symbol error bound of the convolutional codes, and applies to the calculation of the bit error probability of the concatenated codes. Our results are tighter than the earlier studied other bounds.