• The Journal of the Acoustical Society of Korea
• /
• v.28 no.3
• /
• pp.290-297
• /
• 2009

This paper presents an improved adaptive multi-rate wideband (AMR-WB) algorithm for the efficient Text-To-Speech (TTS) database compression. The proposed algorithm includes unnecessary common bit-stream (CBS) removal and parameter delta coding combined with speaker-dependent huffman coding to reduce the required bit-rate without any quality degradation. We also propose lossy coding schemes to produce the maximum bit-rate reduction with negligible quality degradation. The proposed lossless algorithm including CBS removal can reduce bit-rate by 12.40% without quality degradation compared with the 12.65 kbps AMR-WB mode. The proposed lossy algorithm can reduce bit-rate by 20.00% with 0.12 PESQ degradation.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.14 no.4
• /
• pp.123-134
• /
• 2004

In this paper a high speed architecture of the RC4 stream cipher is proposed and its FPGA implementation is presented. Compared to the conventional RC4 designs which have long initialization operation or use double or triple S-arrays to reduce latency delay due to S-array initialization phase, the proposed architecture for RC4 stream cipher eliminates the S-array initialization operation using 256-bit valid entry scheme and supports 40/128-bit key lengths with efficient modular arithmetic hardware. The proposed RC4 stream cipher is implemented using Xilinx XCV1000E-6H240C FPGA device. The designed RC4 stream cipher has about a throughput of 106 Mbits/sec at 40 MHz clock and thus can be applicable to WEP processor and RC4 key search processor.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.21 no.5
• /
• pp.35-45
• /
• 2011

The Salsa20/12 stream cipher selected for the final eSTREAM portfolio has a better performance than software implementation of AES using an 8-bit microprocessor with restricted memory space, In the theoretical approach, the evaluation of exploitable timing vulnerability was 'none' and the complexity of side-channel analysis was 'low', but there is no literature of the practical result of power analysis attack. Thus we propose the correlation power analysis attack method and prove the feasibility of our proposed method by practical experiments, We used an 8-bit RISC AVR microprocessor (ATmegal128L chip) to implement Salsa20/12 stream cipher without any countermeasures, and performed the experiments of power analysis based on Hamming weight model.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.6B
• /
• pp.954-961
• /
• 2010

Stream cipher was worse than block cipher in terms of security, but faster in execution speed as an advantage. However, since so far there have been many algorithm researches about the execution speed of block cipher, these days, there is almost no difference between them in the execution speed of AES. Therefore an secure and fast stream cipher development is urgently needed. In this paper, we propose a 32bit output fast stream cipher, AA32, which is composed of ASR(Arithmetic Shifter Register) and simple logical operation. Proposed algorithm is a cipher algorithm which has been designed to be implemented by software easily. AA32 supports 128bit key and executes operations by word and byte unit. As Linear Feedback Sequencer, ASR 151bit is applied to AA32 and the reduction function is a very simple structure stream cipher, which consists of two major parts, using simple logical operations, instead of S-Box for a non-linear operation. The proposed stream cipher AA32 shows the result that it is faster than SSC2 and Salsa20 and satisfied with the security required for these days. Proposed cipher algorithm is a fast stream cipher algorithm which can be used in the field which requires wireless internet environment such as mobile phone system and real-time processing such as DRM(Digital Right Management) and limited computational environments such as WSN(Wireless Sensor Network).

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.8
• /
• pp.34-40
• /
• 1992

This paper shows a new relational formula of multiplexing gain versus variable input bit rates useful for designing Nx1 ATM(Asynchronous Transfer Mode) multiplexer which mixes several asynchronous bit streams with different transmission rates. The relation between multiplexing gain and input bit stream speeds is derived from the occupied mean lenght(the width per unit time) of cells and the occupation probability of the number of cells at an arbitrary instant when the rates of the periodic cell strams change randomly. And the relation between multiplexing gain and variable bit rates from different number of input bit streams is analyzed accordingly. Under the condition of unlimited multiplexing speed, the more number of input bit streams increases, the bigger the multiplexing gain becomes. While for the case which restricts the multiplexing speed to a limited value, the multiplexing gain becomes smaller contrarily as the number of input bit streams continues too invrease beyond a boundary value. It is shown that for designing an ATM multiplexer according to the latter case, the combination of input bit streams should be determined such as its total bit rate is lower thean, but most apprpaximate to, the multiplexed output speed. Also the general formula evaluating the most significant parameters which should be needed to design the multiplexer is derived.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.5A
• /
• pp.726-742
• /
• 2000

A novel rte control algorithm consisting of two major components, i.e. a variable encoding frame rate method and a hybrid DCT/wavelet I-frame coding scheme, is proposed in this work for low bit rate video coding. Most existing rate control algorithms for low bit rate video focus on bit allocation at the macroblock level under a constant frame rate assumption. The proposed rate control algorithm is able to adjust the encoding frame rate at the expense of tolerable time-delay. Furthermore, an R-D optimized hybrid DCT/wavelet scheme is used for effective I-frame coding. The new rate-control algorithm attempts to achieve a good balance between spatial quality and temporal quality to enhance the overall human perceptual quality at low bit rates. It is demonstrated that the rate control algorithm achieves higher coding efficiency at low bit rates with a low additional computational cost. The variable frame rate method and hybrid I-frame coding scheme are compatible with the bi stream structure of H.263+.

• The KIPS Transactions:PartC
• /
• v.8C no.2
• /
• pp.164-172
• /
• 2001

최근 인터넷의 확산과 더불어 디지털 비디오 라이브러리(DVL : Digital Video Library) 서비스에 대한 관심이 고조되고 있다. 그러나 현재의 통신망 대역폭과 스위칭 환경 하에서는 종단간 QoS 보장하는데 많은 제약사항이 존재한다. 따라서 본 논문에서는 비디오 스트림 처리를 효율적으로 수행하여, 지연-처리율 특성을 만족할 수 있는 스트림 스위칭 구조를 제안하고 이에 대한 성능을 분석하였다. 제안된 ATM-기반 스트림 스위치는 각각 다중화되는 CBR(Constant Bit Rate) 및 VBR(Variable Bit Rate) 스트림의 QoS(Quality of Service)를 보장해야만 한다. 성능분석 결과는 제안된 스위치의 처리율이 r=4일 때 약 0.996의 값을 보였으며, 지연시간도 부하가 0.7 이하일 때 2미만으로 특정되었다. 이 결과는 제안된 구조가 적당한 입력 스트림의 그룹핑을 통하여 비디오 응용을 위한 처리율 및 지연 요구사항 QoS를 보장할 수 있음을 보여준다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 1998.06b
• /
• pp.5-9
• /
• 1998

In this paper, we propose an error-resilient transmission technique for the H.263 video data stream over wireless networks. The proposed algorithm employs bit rearrangement hierarchically, providing the robust and exact synchronization against the bit errors, without requiring extra redundant information. In addition, we propose the recovery algorithm for the lost or erroneous motion vectors. We implement the encoder and decoder, based on the H.263 standard, and evaluate the proposed algorithm through intensive computer simulation. The experimental results demonstrate that the proposed algorithm yields good image quality, in spite of the channel errors, and prevents the error propagation both in the spatial and the temporal domain efficiently.

• Journal of the Institute of Convergence Signal Processing
• /
• v.2 no.3
• /
• pp.9-15
• /
• 2001

Very low bit rate video coding uses the inter-picture video coding method for high compression. The inter-picture video coding is coded based on the information of the previous frames so any packet loss can lead to reduce the image quality on the transmission. In this paper, we proposed the multi-stream generation method for inter-media synchronization of very low bit rate video based on TCP for reliable transmission. The proposed approach performs a reliable transmission via a TCP based protocol. This method incorporates multi-streams in order to enhance the robustness of delivery and can withstand against network jitter. Moreover, the client bandwidths are fully utilized in a highly efficient way.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.54-60
• /
• 2006

In order to test the board with IEEE 1149.1 boundary scan design, the test sequence must be applied as the bit stream However it is very tedious job to generate the test bit sequence since it requires the complete hlowledge about the 1149.1. This fuper introduces a convenient PCI/USB interface controller, named as Test-Ready PCI (TRPCI) ard Test-Ready USB (TRUSB). Test Bus Controller has been developed by TI and Lucent aiming to generate the test bit stream as an instruction level, thus even the novice test engineer can easily generate the test sequence.