• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.190-192
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• 2004

In this paper, we propose a low bit-rate embedded video compression scheme with 3-D block partition coding in the wavelet domain. The proposed video compression scheme includes multi-level 3-dimensional dyadic wavelet decomposition, raster scanning within each subband, formation of block, 3-D partitioning of block, and adaptive arithmetic entropy coding. Although the proposed video compression scheme is quit simple, it produces bit-stream with good features, including SNR scalability from the embedded nature. Experimental results demonstrate that the proposed video compression scheme is quit competitive to other good wavelet-based video coders in the literature.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.80-86
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• 2006

In this paper, we propose the PingPong-128(PP-128) keystream generator, based on summation generator. Proposed PingPong-128, a specific cipher of the PingPong Family, takes 128 bits key and 128 bit initial vector, has 258 bit internal state, and achieves a security level of 128 bits. The security analysis of PingPong-128 is presented, including the resistence to known attacks against the summation generator and other clock-controlled generators.

• Journal of the Chungcheong Mathematical Society
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• v.28 no.2
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• pp.331-343
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• 2015

Invertible transformations over n-bit words are essential ingredients in many cryptographic constructions. When n is large such invertible transformations are usually represented as a composition of simpler operations such as linear functions, S-P networks, Feistel structures and T-functions. Among them we study T-functions which are probably invertible transformations and are very useful in stream ciphers. In this paper we study the number of single cycle T-functions satisfying some conditions and characterize single cycle T-functions on $(\mathbb{Z}_2)^n$ generated by some elements in $(\mathbb{Z}_2)^{n-1}$.

• Journal of the Optical Society of Korea
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• v.18 no.1
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• pp.65-70
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• 2014

This paper presents the simulation and design of an all-optical subtractor using a quantum-dot semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA MZI) structure consisting of two cascaded switches, the first of which produces the differential bit. Then the second switch produces the borrow bit by using the output of the first switch and the subtrahend data stream. Simulation results were obtained by solving the rate equations of the QD-SOA. The effects of QD-SOA length, peak power and current density have been investigated. The designed gate can operate at speeds of over 250 Gb/s. The simulation results demonstrate a high extinction ratio and a clear and wide-opening eye diagram.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10a
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• pp.151-154
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• 2001

본 연구는 웹 카메라에 적용하기 위한 JPEG2000의 주요 블록인 EBCOT(Embedded Block Coding with Optimized Truncation)의 설계 및 구현에 관한 연구이다. EHCOT 블록은 웨이블렛(wavelet)변환에 의해 분할된 각 sub-band에 존재하는 주위 화소 값들과 상위 bit-plane의 값들에 대한 상호 연관성을 조사하여 context을 추출하고 그 context를 이용하여 엔트로피 부호화(entropy coding)를 수행하는 T1(Tier 1) 블록과 bit-stream을 구성하는 T2(Tier 2) 블록으로 구성된다. 본 논문에서는 JPEG2000에서 전체 압축성능을 좌우하는 EBCOT의 T1 블록을 Synopsys tool을 이용하여 설계하고 구현하였다.

• Journal of the Chungcheong Mathematical Society
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• v.24 no.4
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• pp.927-934
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• 2011

Invertible transformations over n-bit words are essential ingredients in many cryptographic constructions. When n is large (e.g., n = 64) such invertible transformations are usually represented as a composition of simpler operations such as linear functions, S-P networks, Feistel structures and T-functions. Among them we study T-functions which are probably invertible and are very useful in stream ciphers. In this paper we study some conditions on a T-function h(x) such that f(x) = x + h(x) has a single cycle on ${\mathbb{Z}}_{2^n}$.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.436-438
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• 2002

인터넷 기술이 반전함에 따라서 인터넷을 통한 서비스에 대한 관심도가 증가되고 있다. 특히 멀티미디어 서비스인 경우 QoS(Quality of Service)를 보장해야 만다. 그런데 제한된 대역폭 내에서 전송량이 급격히 증가하는 경우 네트워크 자원의 이용도와 서비스의 품질에 큰 영향을 준다. 이에 스무딩 기법은 가변 비트율(VBR : Variable Bit Rate)을 가진 비디오 스트림(Stream)을 전송할 때 네트워크 자원의 이용도와 서비스의 품질 저하를 막기 위해 전송률(Transmission rate)을 일정하게 유지시키는 기법으로 서버와 네트워크 사이의 중간노드에서 수행된다. 본 논문에서 스무딩 알고리즘을 프레임 단위로 저리할 경우 해당자원의 과부하가 탄생하므로 이를 개선한 스무딩 알고리즘을 제안하고, 기존 스무딩 알고리즘의 시간 복잡도와 성능을 중심으로 비교 분석하였다.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.251-253
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• 2005

In this paper, an adaptive algorithm is proposed in streaming MPEG-4 contents with fluctuating resource amount such as throughput of network conditions. MPEG-4 is the international standard for audiovisual presentation which is composed of object based media streams. The proposed technique provides the media stream corresponding an object with multiple media streams with different qualities and bit rate in order to support object based scalability to the MPEG-4 content. In addition, making the object streams adaptable, a feasible stream set selected from the multiple streams for transmission with optimal quality in the form of the current status.

• Proceedings of the Korea Contents Association Conference
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• 2004.11a
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• pp.344-347
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• 2004

Critical cryptography applications require the production of an unpredictable and unbiased stream of binary data derived from a fundamental noise mechanism. In this paper, we proposed a RNG with Gaussian noise using filter algorithm. The proposed scheme is designed to reduce the statistical property of the biased bit stream in the output of a RNG. Experimental show that we analysis the loss rate according to window size and propose optimum window size.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1304-1307
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• 2002

In this paper, we describe the structure and the test results of a Bluetooth baseband module we have developed. The module has a distributed buffer, i.e. FIFO, for data stream. Bus interface of the module is designed on the basis of interface of microprocessor widely used and the external interface is designed to consider chips connected directly. Since the module performs as many hardware efficient tasks as possible, processing load of microprocessor is very small. It can also be controlled either by software or by hardware for flexibility. The fully synthesizable baseband module was fabricated in a $0.25\mu\textrm{m}$ CMOS technology occupying $2.79\times2.8{\textrm{mm}^2}$ area. And an FPGA implementation of this module is tested for file and bit-stream transfers between PCs.