• Journal of Broadcast Engineering
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• v.8 no.1
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• pp.45-53
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• 2003

Traffic specification plays a crucial role in the resource reservation for video services over the packet-switching networks. The current development of QoS-guaranteed service still leaves a wide space for the selection of traffic specification. We propose a new method to estimate the traffic specification of variable-bit-rate (VBR) video for deterministic service. The method is based on the concept of empirical envelope and the delay bound. The solution shows to be simple yet it provides excellent network utilization.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.176-178
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• 1988

In this paper, techniques of constructing parity check matrix of SBEC-DBED codes will be presented to improve reliability of muliti-bit-per-chip type memory systems. And the high speed parallel CODEC of (88.64)SBEC-DBED code which is applicable to real system will be designed.

• Journal of Scientific & Technological Knowledge Infrastructure
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• s.7
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• pp.134-140
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• 2001

To know about the performance of KREONET, we installed an active network performance measurement tool, PingER. For customization, we modified its architecture and some codes. Although this customization is a minor change of PingER, it gives much benefit and convenience for both operators and users. Using PingER, we can measure the effect of the STAR TAP link. The new networking through the link is a little bit slower than the previous networking. But the new link shows far fewer packet losses and provides more reliable networking.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.812-820
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• 2006

Ethernet has been given a greater attention recently due to tendency of unifying most of transmission technique(not only LAN, but MAN and WAN) to ethernet. Performance evaluation was performed using C language for 10Gbps ethernet Data Link to design the optimum hardware, then internal FIFO size was evaluated. In this paper, MAC core for 10Gbps ethernet which contains high layer interface, transmit engine, flow control block, receive engine, reconciliation sublayer, configuration block, statistics block, and XGMII interface block was designed using VHDL language and Xilinx 6.2i tool and verified using Model_SIM 5.7G simulator. According to the specification of 10Gbps ethernet, MAC core with 64-bit data path should support 156.25MHz in order to support 10Gbps. The designed MAC core that process 64-bit data, operates at 168.549MHz and hence supports the maximum 10.78Gbps data processing. The designed MAC core is applicable to an area that needs a high-speed data processing of 10Gbps or more.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.19-25
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• 2005

This paper describes a synthesis method for a self-equalized dual-passband filter. Compared to conventional dual-passband filter, a self-equalized dual-passband filter can reduce BER(bit error rate) in digital data communications and does not need an external equalizer for group-delay equalization. To validate the synthesis technique, a 10-pole dual-mode dual-passband filter which has two self-equalized 5-pole elliptic response passband is synthesized.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.224-229
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• 2008

In the paper, a new Constraint algorithm is proposed to solve the fan-in problem occurred in the encoding circuitry of an ADC. The Flash ADC architecture uses a Double-Base Number System(DBNS). The DBNS has been known to represent the Multidimensional Logarithmic Number System (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in Digital Signal Processing (DSP) applications. The authors use the DBNS with the base 2 and 3 in designing ADC encoder circuits, which is called as Double Base Integer Encoder(DBIE). A symmetric map is analyzed first, and then asymmetric map is followed to provide addition ready DBNS for DSP circuitry. The simulation results of the DBIE circuits in 6-bit and 8-bit ADC show the effectiveness of the Constraint algorithm with $0.18{\mu}m$ CMOS technology. The DBIE yields faster processing speed compared to the speed of Fat Tree Encoder (FAT) circuits by 17% at more power consumption by 39%.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.2
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• pp.48-56
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• 2009

We propose a fast intra mode skip decision algorithm for H.264/AVC video encoding. Although newly added MB encoding algorithms based on various prediction methods increase compression ratio, they require a significant increase in the computational complexity because we calculate rate-distortion(RD) cost for all possible MB coding modes and then choose the best one. In this paper, we propose a fast mode decision algorithm based on an adaptive motion vector map(AMVM) method for H.264/AVC video encoding to reduce the processing time for the inter frame. We verify that the proposed algorithm generates generally good performances in PSNR, bit rates, and processing time.

• The KIPS Transactions:PartD
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• v.9D no.4
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• pp.579-586
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• 2002

This paper propose an efficient algorithm for mining association rules in the large main memory systems. To do this, the paper attempts firstly to extend the conventional algorithms such as DHP and Partition in order to be compatible to the large main memory systems and proposes secondly an algorithm to improve Partition algorithm by applying the techniques of the hash table and the bit map. The proposed algorithm is compared to the extended DHP within the experimental environments and the results show up to 65% performance improvement in comparison to the expanded DHP.

• The Journal of the Korea Contents Association
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• v.12 no.4
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• pp.31-39
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• 2012

DVC(Distributed Video Coding) techniques have been attracting a lot of research works since these enable us to implement the light-weight video encoder and to provide good coding efficiency by introducing the feedback channel. However, the feedback channel causes the decoder to increase the decoding complexity and requires very high decoding latency because of numerous iterative decoding processes. So, in order to reduce the decoding delay and then to implement in a real-time environment, this paper proposes several parity bit estimation methods which are based on the temporal correlation, spatial correlation and spatio-temporal correlations between LDPCA frames on each bit plane in the consecutive video frames in pixel-domain Wyner-Ziv video coding scheme and then the performances of these methods are compared in fast DVC scheme. Through computer simulations, it is shown that the adaptive spatio-temporal correlation-based estimation method and the temporal correlation-based estimation method outperform others for the video frames with the highly active contents and the low active contents, respectively. By using these results, the proposed estimation schemes will be able to be effectively used in a variety of different applications.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.