• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제10권11호
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• pp.5381-5399
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• 2016

Currently, the quantize-and-forward (QF) scheme with high order modulation and quantization has rather high complexity and it is thus impractical, especially in multiple relay cooperative communications. To overcome these deficiencies, an improved low complex QF scheme is proposed by the combination of the low order binary phase shift keying (BPSK) modulation and the 1-bit and 2-bit quantization, respectively. In this scheme, the relay selection is optimized by the best relay position for best bit-error-rate (BER) performance, where the relays are located closely to the destination node. In addition, an optimal power allocation is also suggested on a total power constraint. Finally, the BER and the achievable rate of the low order 1-bit, 2-bit and 3-bit QF schemes are simulated and analyzed. Simulation results indicate that the 3-bit QF scheme has about 1.8~5 dB, 4.5~7.5 dB and 1~2.5 dB performance gains than those of the decode-and-forward (DF), the 1-bit and 2-bit QF schemes, at BER of $10^{-2}$, respectively. For the 2-bit QF, the scheme of the normalized Source-Relay (S-R) distance with 0.9 has about 5dB, 7.5dB, 9dB and 15dB gains than those of the distance with 0.7, 0.5, 0.3 and 0.1, respectively, at BER of $10^{-3}$. In addition, the proposed optimal power allocation saves about 2.5dB much more relay power on an average than that of the fixed power allocation. Therefore, the proposed QF scheme can obtain excellent features, such as good BER performance, low complexity and high power efficiency, which make it much pragmatic in the future cooperative communications.

• 한국컴퓨터정보학회논문지
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• 제23권8호
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• pp.75-84
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• 2018

In this research, a bit correction technique of data hiding method in timestamp of MFT entry in NTFS file system is proposed. This method is proposed in two ways, depending on the number of bytes of data to hide. A basic data hiding method using a bit correction technique to solve the problems of the conventional 2-byte technique is proposed. In order to increase the capacity of the data, a 3-byte data hiding method using an extended bit correction technique is proposed. The data hiding method in the timestamps is based on the fact that is not revealed in the Windows explorer window and the command prompt window even if any data is hidden in the timestamp area of less than one second. It is shown that the validity of the proposed method through the experimental two cases of the basic data hiding method by the bit correction method and the 3-byte data hiding method by the extended bit correction method.

• 한국멀티미디어학회논문지
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• 제24권8호
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• pp.1012-1019
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• 2021

Currently, since the black-white QR (Quick Response) codes have limited storage capacity, color QR codes have been actively being studied. By multiplexing 3 colors, the color QR codes can allow the code capacity to be increased by three times, however, the color multiplexing brings about the possibility of crosstalk and noises in the acquisition process of the final image, incurring the decrease of bit-recognition rate. In order to improve the bit recognition rate, while keeping the storage capacity high, this paper proposes a new type of color QR code which uses the pattern information as well as the color information, and then analyzes how to increase the bit recognition rate. For this aim, the paper presents an efficient system which extracts embedded information from color QR code and then, through practical experiments, it is shown that the proposed color QR codes improves the bit recognition rate and are useful for commercial applications, compared to the conventional color codes.

• Geomechanics and Engineering
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• 제8권4호
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• pp.477-493
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• 2015

In rock drilling, the most important characteristic to clarify is the wear of the drill bits. The reason that the rock drill bits fail with time is wear. In dry sliding contact adhesive wear deteriorates the materials in contact, quickly, and is the result of shear fracture in the momentary contact joins between the surfaces. This paper aims at presenting an overview of the assessment of WC/Co cemented carbide (CC) tricone bit in rotary drilling. To study wear of these bits, two approaches have been used in this research. Firstly, the new bits were weighted before they mounted on the drill rigs and also after completion their useful life to obtain bit weight loss percentage. The characteristics of the rock types drilled by using such this bit were measured, simultaneously. Alternatively, to measure contact wear, namely, matrix wear a micrometer has been used with a resolution of 0.02 mm at different direction on the tricone bits. Equivalent quartz content (EQC), net quartz content (QC), muscovite content (Mu), coarseness index (CI) of drill cuttings and compressive strength of rocks (UCS) were obtained along with thin sections to investigate mineralogical properties in detail. The correlation between effective parameters and bit wear were obtained as result of this study. It was observed that UCS shows no significant correlation with bit wear. By increasing CI and cutting size of rocks wear of bit increases.

• 대한전자공학회논문지SD
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• 제37권6호
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• pp.1-8
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• 2000

본 논문에서는 플래시 메모리의 비트라인 공유에 따른 간섭현상을 최소화한 센스 엠프를 제시하였다. 외부소자에서 내부 플래시 메모리를 읽고자 하였을 때 발생할 수 있는 간섭현상은 공유된 비트라인으로 인하여 출력에서 에러가 발생할 수 있다. 주된 원인으로는 칩의 소형화에 따른 얇은 부유 게이트 옥사이드층의 사용에 따른 전하의 이동에 따라 발생한다. 본 논문에서는 전하의 이동을 최소화 하기 위해서는 공유된 비트라인에 인가되는 전압을 낮추었으며, 낮은 비트라인 전압으로도 플래시 셀의 데이터의 값을 판정할 수 있는 센스 앰프를 설계, 구현, 검증하였다.

• 한국통신학회논문지
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• 제30권7C호
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• pp.624-632
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• 2005

이 논문에서는 BICM-OFDM(Bit Interleaved Coded modulation-Orthogonal Frequency Division Multiplexing) 시스템을 위한 비트 할당 기법에 대하여 연구한다. 부채널의 상태에 따라 부반송파의 전송 매개 변수를 조절하면 OFDM 시스템의 성능을 크게 개선시킬 수 있다. 여기서는 BICM-OFDM 시스템을 위한 적응 전송 기법으로 데이터 전송률을 일정하게 유지하면서 비트 오류율이 최소가 되도록 부반송파에 비트를 할당한다. 또한, 할당하는 비트 수가 정수인 제한 조건 하에서 최적의 해를 얻기 위해 이산 라그랑지 승수 방법을 사용한다. 모의실험을 통해 제안한 비트 할당 기법의 계산량이 크지 않으며, BICM-OFDM 시스템에 제안한 기법을 사용하면 약 $2\~3$ dB의 신호대 잡음비의 이득을 얻을 수 있음을 보인다.

• 한국통신학회논문지
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• 제28권12B호
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• pp.1091-1099
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• 2003

국가정보원에서 방화벽(Firewall)의 인증을 하고 있고, 여기에서 K4 등급을 받은 방화벽이 모든 공공기관에 설치되고 있다. Solaris를 운영체제로 하는 K4 방화벽의 기능에서 패킷필터링과 NAT, 프락시 및 인증서비스 기능 등에 관해 기능 설정 전과 기능 설정 후의 성능을 비교 평가한다. 그리고 기존 32비트 체제 방화벽성능에 비해 최근 인증을 받고 있는 64비트 체제의 Solaris 방화벽을 비교 평가하여. 32비트에 비해 64비트 체제의 방화벽이 2배 이상 성능 개선이 나타남을 평가한다. 그리고, 결론에서 K4 방화벽 및 대한민국 방화벽의 연구 및 개발에 방향을 제시하여 세계에서 경쟁력 있는 시스템으로 도움이 되고자 한다.

• 한국컴퓨터정보학회논문지
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• 제20권11호
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• 한국군사과학기술학회지
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• 제15권2호
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• pp.111-120
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• 2012

Built-In-Test is a design feature in more and more advanced weapon system. During development test and evaluation(DT&E) it is critical that the BIT system be evaluated. The BIT system is an integral part of the weapon system and subsystem. Built-In-Test assists in conducting on system and subsystem failure detection and isolation to the Line Replaceable Unit(LRU). This capability reduces the need for highly skilled personnel and special test equipment at organizational level, and reduces maintenance down-time of system by shortening Total Corrective Maintenance Time. During DT&E of weapon system the objective of BIT system evaluation is to determine BIT capabilities achieved and to identify deficiencies in the BIT system. As a result corrective actions are implemented while the system is still in development. Through the use of the reiterative BIT evaluation the BIT system design was corrected, improved, or updated, as the BIT system matured.