• Journal of the Institute of Electronics Engineers of Korea SP
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• 제41권1호
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• pp.47-56
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• 2004

This paper describes a new bit allocation algorithm that can achieve a constant bit rate when coding multiple video objects, while improving rate-distortion (R-D) performance over the VM5 method for MPEG-4 object-based video coding. In particular, we propose two models to estimate the rate-distortion characteristics of coded objects as well as skipped objects. Based on the proposed models, we present several R-D coding modes with spatio-temporal trade-offs to improve coding efficiency. The proposed algorithm is performed at the object level for object-based video coding. Simulation results demonstrate moderate improvement at low as well as high bit rates. The proposed algorithm can produce the actual coded bits very close to the target bits over a wide range of bit rates. Consequently, the proposed algerian has not experienced any buffer overflow or underflow over the bit rates between 32 kbps and 256 kbps.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제32A권5호
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제28권7B호
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• pp.628-637
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• 2003

This paper describes a novel multiplexing scheme for delay-sensitive multiple VBR-coded bit streams in live multimedia service offered to high-speed networks. The primary goal of multiplexing in this paper is to keep delay limits of each bit streams and to enhance network resource utilization when they no multiplexed and transmitted over network. For this aim, this paper presents a dynamical control scheme which does not cause violation of any delay constraints to each bit steam. The scheme is based on the assumption that recent behavior of the each bit scream has high correlation with near-term future behavior. Such property is used to make as flat as possible by both temporal averaging on a stream-by-stream and spatial averaging is introduced when multiple VBR-coded bit streams are multiplexed. The effectiveness of the scheme is evaluated by several simulation using an MPEG-coded video trace of Star_wars and it is shown that the proposed scheme can effectively reduce the feat rate md coefficient of variation of the multiplexed transmission rate.

• Journal of Broadcast Engineering
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• 제21권6호
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• pp.929-943
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• 2016

This paper proposes the rate control algorithm based on the S-JND (Saliency-Just Noticeable Difference) model for considering perceptual visual quality. The proposed rate control algorithm employs the S-JND model to simultaneously reflect human visual sensitivity and human visual attention for considering characteristics of human visual system. During allocating bits for CTU (Coding Tree Unit) level in a rate control, the bit allocation model calculates the S-JND threshold of each CTU in a picture. The threshold of each CTU is used for adaptively allocating a proper number of bits; thus, the proposed bit allocation model can improve perceptual visual quality. For performance evaluation of the proposed algorithm, the proposed algorithm was implemented on HM 16.9 and tested for sequences in Class B and Class C under the CTC (Common Test Condition) RA (Random Access), Low-delay B and Low-delay P case. Experimental results show that the proposed method reduces the bit-rate of 2.3%, and improves BD-PSNR of 0.07dB and bit-rate accuracy of 0.06% on average. We achieved MOS improvement of 0.03 with the proposed method, compared with the conventional method based on DSCQS (Double Stimulus Continuous Quality Scale).

• Journal of KIISE:Databases
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• 제31권2호
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• pp.108-121
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• 2004

In this paper, we propose an enhanced snapshot technique that solves performance degradation when snapshot is initiated for the storage cluster system. However, traditional snapshot technique has some limits adapted to large amount storage shared by multi-hosts in the following aspects. As volume size grows, (1) it deteriorates crucially the performance of write operations due to additional disk access to verify COW is performed. (2) Also it increases excessively the blocking time of write operation performed during the snapshot creation time. (3)Finally, it deteriorates the performance of write operations due to additional disk I/O for mapping block caused by the verification of COW. In this paper, we propose an efficient snapshot technique for large amount storage shared by multi-hosts in SAN Environments. We eliminate the blocking time of write operation caused by freezing while a snapshot creation is performing. Also to improve the performance of write operation when snapshot is taken, we introduce First Allocation Bit(FAB) and Snapshot Status Bit(SSB). It improves performance of write operation by reducing an additional disk access to volume disk for getting snapshot mapping block. We design and implement an efficient snapshot technique, while the snapshot deletion time, improve performance by deallocation of COW data block using SSB of original mapping entry without snapshot mapping entry obtained mapping block read from the shared disk.

• Journal of IKEEE
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• 제10권2호통권19호
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• pp.134-140
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• 2006

This paper proposed a low power resource allocation algorithm for the minimum switching activity of operators in high level synthesis. In this paper, the proposed method finds switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity was found the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and maximal control step. And it is the reduction effect from 8.5% to 9.3%.

• The Journal of the Acoustical Society of Korea
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• 제21권1호
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• pp.5-10
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• 2002

This paper proposes new 16 kbps wideband speech codec with bandwidth of 7 kHz. The proposed codec decomposes the input speech signal into low-band and high-band signals using QMF (Quadrature Mirror Filter), then AMR (Adaptive Multi Rate) speech codec processes the low-band signal and new transform-domain codec based on G.722.1 wideband cosec compresses the high-band signal. The proposed codec allocates different number of bits to each band in an adaptive way according to the property of input signal, which provides better performance than the codec with the fixed bit allocation scheme. In addition, the proposed cosec processes high-band signal using wavelet transform for better performance. The performance of proposed codec is measured in a subjective method. and the simulations with various speech data show that the proposed coders has better performance than G.722 48 kbps SB-ADPCM.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제37권4A호
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• pp.227-238
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• 2012

In this paper, we propose a practical time-division half-duplex Estimate and Forward (EF) relaying protocol. The conventional EF relaying protocol works well only when the relay node is near the destination node. The proposed EF relaying protocol, however, determines adaptively relay parameters such as the quantization level of relay node and the power allocation between source and relay nodes according to the channel conditions. By doing so, the proposed EF relaying protocol provides low probability of bit error even when the relay node is far from the destination node. Consequently, the proposed EF protocol is suitable for the mobile relay systems. It is shown by simulations that the proposed EF relaying protocol shows lower bit error rate for all relay positions than a conventional EF protocol.

• Journal of Broadcast Engineering
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• 제22권3호
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• pp.381-396
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• 2017

In this paper, the perceptual rate control algorithm is studied for HEVC (High Efficiency Video Coding) encoder with bit allocation based on perceived visual quality. This paper proposes perceptual rate control algorithm which could consider perceived quality for HEVC encoding method. The proposed rate control algorithm employs adaptive bit allocation for frame and CTU level using the perceived visual importance of each CTU. For performance evaluation of the proposed algorithm, the proposed algorithm was implemented on HM 16.9 and tested for sequences in Class B under the CTC (Common Test Condition) RA (Random Access) case. Experimental results show that the proposed method reduces the bitrate of 3.12%, and improves BD-PSNR of 0.08dB and bitrate accuracy of 0.07% on average. And also, we achieved MOS improvement of 0.16 with the proposed method, compared with the conventional method based on DSCQS (Double Stimulus Continuous Quality Scale).

• The Journal of Korean Institute of Communications and Information Sciences
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• 제37권1C호
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• pp.45-53
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• 2012

In this paper, we proposed the efficient addressing scheme for improving the performance of routing algorithm by using ZigBee in Smart Grid environment. A distributed address allocation scheme used an existing algorithm that has wasted in address space. Therefore proposing x, y and z coordinate axes from divided address space of 16 bit to solve this problems. Each node was reduced not only bitwise but also multi hop using the coordinate axes while routing than $Cskip$ algorithm. I compared the performance between the standard and the proposed mechanism through the numerical analysis. Simulation verified performance about decrease averaging multi hop count that compare proposing algorithm and another. The numerical analysis results show that proposed algorithm reduced the multi hop better than ZigBee distributed address assignmen.