• KEPCO Journal on Electric Power and Energy
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• v.6 no.2
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• pp.119-122
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• 2020

With recent ESS (Energy Storage System) fire accident, the fault protection performance is becoming more important. However, there has never been any experiments with the protection performance on the faults in the ESS system level. In this study, the effect of AC ground fault and IGBT (Insulated Gate Bipolar mode Transistor) short-circuit failure on MW class ESS was performed experimentally for the first time in the world. First of all, the effect of the AC single line ground fault on battery was analyzed. Moreover, the transient voltage was investigated as a function of the battery capacity and the power level. Finally, the breaking capability and insulation performance of ESS were examined under PCS short-circuit fault condition. Through the tests, it was found that ESS protection system safely blocked the faulty current regardless of the faults, whereas the electronic parts such as IGBT and MC (Magnetic Contactor) were broken by the fault current. Also, the electrical breakdown in ESS resulted from the transient voltage during the protection process.

• ETRI Journal
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• v.37 no.6
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.3
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• pp.135-140
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• 2016

In this study, we developed the solution-processed PMMA-$HfO_x$ hybrid ReRAM devices to overcome the respective drawbacks of organic and inorganic materials. The performances of PMMA-$HfO_x$ hybrid ReRAM were compared to those of PMMA- and $HfO_x$-based ReRAMs. Bipolar resistive switching behavior was observed from these ReRAMs. The PMMA-$HfO_x$ hybrid ReRAMs showed a larger operation voltage margin and memory window than PMMA-based and $HfO_x$-based ReRAMs. The reliability and electrical instability of ReRAMs were remarkably improved by blending the $HfO_x$ into PMMA. An Ohmic conduction path was commonly generated in the LRS (low resistance state). In HRS (high resistance state), the PMMA-based ReRAM showed SCLC (space charge limited conduction). the PMMA-$HfO_x$ hybrid ReRAM and $HfO_x$-based ReRAM revealed the Pool-Frenkel conduction. As a result of flexibility test, serious defects were generated in $HfO_x$ film deposited on PI (polyimide) substrate. On the other hand, the PMMA and PMMA-$HfO_x$ films showed an excellent flexibility without defect generation.

• ETRI Journal
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• v.39 no.5
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• pp.746-755
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• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

• Journal of Sensor Science and Technology
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• v.24 no.5
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• pp.353-357
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• 2015

A new SPICE-compatible model for a gate/body-tied PMOSFET photodetector (GBT PD) with an overlapping control gate is presented. The proposed SPICE-compatible model of a GBT PD with an overlapping control gate makes it possible to control the photocurrent. Research into GBT PD modeling was proposed previously. However, the analysis and simulation of GBT PDs is not lacking. This SPICE model concurs with the measurement results, and it is simpler than previous models. The general GBT PD model is a hybrid device composed of a MOSFET, a lateral bipolar junction transistor (BJT), and a vertical BJT. Conventional SPICE models are based on complete depletion approximation, which is more applicable to reverse-biased p-n junctions; therefore, they are not appropriate for simulating circuits that are implemented with a GBT PD with an overlapping control gate. The GBT PD with an overlapping control gate can control the sensitivity of the photodetector. The proposed sensor is fabricated using a $0.35{\mu}m$ two-poly, four-metal standard complementary MOS (CMOS) process, and its characteristics are evaluated.

• Journal of the Korean institute of surface engineering
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• v.46 no.5
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• pp.192-196
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• 2013

Stainless steels (AISI 316L) are carburized by Inductively coupled plasma using $CH_4$ and Ar gas. The ${\gamma}_c$ phase(S-phase) is formed on the surface of stainless steel after carburizing process. The XRD peak of carburized samples is shifted to lower diffracting angle due to lattice expansion. Overall, the thickness of ${\gamma}_c$ phase showed a linear dependence with respect to increasing temperature due to the faster rate of diffusion of carbon. However, at temperatures above 500, the thickness data deviated from the linear trend. It is expected that the deviation was caused from atomic diffusion as well as other reactions that occurred at high temperatures. The interfacial contact resistance (ICR) and corrosion resistance are measured in a simulated proton exchange membrane fuel cell (PEMFC) environment. The ICR value of the carburized samples decreased from 130 $m{\Omega}cm^2$ (AISI 316L) to about 20 $m{\Omega}cm^2$. The sample carburized at 200 showed the best corrosion current density (6 ${\mu}Acm^{-2}$).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1890-1896
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• 2008

In this paper, the Si vertical Hall devices ale fabricated by using standard bipolar process and investigated in terms of the opeating and noise properties. The sensitivity of device with P+ isolation dam(type B) has been increased up to about 1.2 times compared to that device without the dam also noise has been increased. With the condition of f=I[KHz], band-width 1[Hz], the resolution of magnetic-field detection were about $0.97[{\mu}T]$/ type B and $1.25[{\mu}T]$/ type A, respectively, thus we must consider correlation the low noise or good resolution and high sensitivity in the situation for device geometry design or even for the materials.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.1710-1716
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• 2008

The Loop Heat Pipe (LHP) operates to pump the working fluid by means of the capillary force in a wick structure. Particularly, it is difficult to design and manufacture the evaporator consisted of a grooved container and a compensation chamber as well as the wick structure. This study is related to design and manufacture the grooved container coupled with wick structure, the properties of the wick structure such as the permeability, the porosity, and the maximum capillary pressure were measured to apply the cooling technology for Insulated Gate Bipolar Transistor (IGBT). The container of the LHP was manufactured by the electrical discharge process and the wick structure was sintered with the nickel particle by an axial-press apparatus with the pulse electronic discharge. As results, the properties of the wick were experimentally obtained about 60% of the porosity, 35kPa of the maximum capillary force and $1.53{\times}10-13m2$ of the permeability.

• Journal of IKEEE
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• v.11 no.4
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• pp.158-164
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• 2007

In this study, three types of a novel Trench IGBTs(Insulated Gate Bipolar Transistor) are proposed. The first structure has P-collector which is isolated by $SiO_2$ layer to enhance anode-injection-efficiency and enable the device to have a low on-state voltage drop(Von). And the second structure has convex P-base region between both gates. This structure may be effective to distributes electric-field crowded to gate edge. So this structure can have higher breakdown voltage(BV) than conventional trench-type IGBT(TIGBT). The process and device simulation results show improved on-state, breakdown and switching characteristics in each structure. The first one was presented lower on state voltage drop(2.1V) than that of conventional one(2.4V). Also, second structurehas higher breakdown voltage(1220V) and faster turn off time(9ns) than that of conventional structure. Finally, the last one of the proposed structure has combined the two structure (the first one and second one). This structure has superior electric characteristics than conventional structure about forward voltage drop and blocking capability, turnoff characteristics.

• Journal of the Korean Vacuum Society
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• v.12 no.4
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• pp.239-250
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• 2003

The reliability degradation phenomena in the SiGe hetero-junction bipolar transistor (HBT) are investigated in this review. In the case of the SiGe HBT the decrease of the current gain, the degradation of the AC characteristics, and the offset voltage are frequently observed, which are attributed to the emitter-base reverse bias voltage stress, the transient enhanced diffusion, and the deterioration of the base-collector junction due to the fluctuation in fabrication process, respectively. The reverse-bias stress on the emitter-base junction causes the recombination current to rise, increasing the base current and degrading the current gain, because hot carriers formed by the high electric field at the junction periphery generate charged traps at the silicon-oxide interface and within the oxide region. Because of the enhanced diffusion of the dopants in the intrinsic base induced by the extrinsic base implantation, the shorter distance between the emitter-base junction and the extrinsic base than a critical measure leads to the reduction of the cut-off frequency ($f_t$) of the device. If the energy of the extrinsic base implantation is insufficient, the turn-on voltage of the collector-base junction becomes low, in the result, the offset voltage appears on the current-voltage curve.