• The Journal of the Korea Contents Association
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• v.9 no.12
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• pp.52-63
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• 2009

The problem of scheduling simply periodic task systems upon a uniform multiprocessor is considered. Partitioning of periodic task systems requires solving the bin-packing problem, which is known to be intractable (NP-hard in the strong sense). This paper presents a global scheduling algorithm which transforms a given simply periodic task system into another using a "task-splitting" technique. Each transformed simply periodic task system is guaranteed to be successfully scheduled upon any uniform multiprocessor using a partitioned scheduling algorithm. It is proven that the proposed algorithm achieves the theoretical maximum utilization bound upon any uniform multiprocessor platform.

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.15-24
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• 1999

In this paper, we propose a new CPLD technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result. it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB.

• Journal of Advanced Navigation Technology
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• v.16 no.3
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• pp.488-494
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• 2012

This paper classifies the self-defense techniques used by the malicious software based on their approaches, introduces the packing technique as one of the code protection methods and proposes a way to quickly analyze the packed malicious codes. Packing technique hides a malicious code and restore it at runtime. To analyze a packed code, it is initially required to find the entry point after restoration. To find the entry point, it has been used reversing the packing routine in which a jump instruction branches to the entry point. However, the reversing takes too much time because the packing routine is usually obfuscated. Instead of reversing the routine, this paper proposes an idea to search some features of the startup code in the standard library used to generate the malicious code. Through an implementation and a consequent empirical study, it is proved that the proposed approach is able to analyze malicious codes faster.

• IE interfaces
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• v.21 no.1
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• pp.8-17
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• 2008

A new search procedure, VLT(Vertex Line Tracing) heuristic, for two dimensional irregular shapes nesting problem was suggested in this study. The VLT heuristic was suggested to the nesting problem to overcome disadvantages of the existing NFP(No-Fit-Polygon) method. This VLT heuristic was compared with the results of the existing benchmark problems suggested by Albano, Hopper, and Burke. The results of the VLT heuristic give efficient solutions in the point of the scrap ratio and computation time. A computer program, NestLogic, using C++ for VLT heuristic was also developed for this nesting problem.

• Journal of the Korea Society of Computer and Information
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• v.19 no.10
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• pp.169-173
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• 2014

Nobody has yet been able to determine the optimal solution conclusively whether NP-complete problems are in fact solvable in polynomial time. Gu$\acute{e}$ret et al. tries to obtain the optimal solution using linear programming with $O(m^4)$ time complexity for barge loading problem a kind of bin packing problem that is classified as nondeterministic polynomial time (NP)-complete problem. On the other hand, this paper suggests the loading rule of profit priority rank algorithm with O(m log m) time complexity. This paper decides the profit priority rank firstly. Then, we obtain the initial loading result using the rule of loading the good has profit priority order. Finally, we balance the loading and capability of barge swap the goods of unloading in previously loading in case of under loading. As a result of experiments, this algorithm reduces the $O(m^4)$ of linear programming to O(m log m) time complexity for NP-complete barge loading problem.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.9-17
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• 1999

In this paper, we propose a new technology mapping algorithm for CPLD under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces delay time and the number of CLBs much more than the existing tools of technology mapping algoritm.

• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.11-18
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• 2005

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint. This algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by $62.2\%$ than those of DDMAP. And reduced the number of CLBs by $17.6\%$ than those of TEMPLA.

• Journal of the Korea Society of Computer and Information
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• v.4 no.3
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• pp.35-46
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• 1999

In this paper, we propose a new CPLD technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm. a given logic equation is constructed as the DAG type. then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also. after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within Cl.B. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time much more than the TMCPLD.

• Journal of the Korea Society of Computer and Information
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• v.20 no.1
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• pp.111-118
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• 2015

This paper deals with the routing and wavelength assignment problem (RWAP) that decides the best lightpaths for multiple packet demands for (s,t) in optical communication and assigns the minimum number of wavelengths to given lightpaths. There has been unknown of polynomial-time algorithm to obtain the optimal solution for RWAP. Hence, the RWAP is classified as NP-complete problem and one can obtain the approximate solution in polynomial-time. This paper decides the shortest main and alternate lightpath with same hop count for all (s,t) for given network in advance. When the actual demands of communication for particular multiple packet for (s,t), we decrease the maximum utilized edge into b utilized number using these dual-paths. Then, we put these (s,t) into b-wavelength bins without duplicated edge. This algorithm can be get the optimal solution within O(kn) computational complexity. For two experimental data, the proposed algorithm shows that can be obtain the known optimal solution.

• Journal of the Korea Society of Computer and Information
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• v.27 no.9
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• pp.59-68
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• 2022

A recommender system covers users, searches the items or services which users will like, and let users purchase them. Because recommendations from a recommender system are predictions of users' preferences for the items which they do not purchase yet, it is rarely possible to be drawn a perfect answer. An evaluation has been conducted to determine whether a prediction is right or not. However, it can be lower user's satisfaction if a recommender system focuses on only the preferences, that is caused by a 'filter bubble effect'. The filter bubble effect is an algorithmic bias that skews or limits the information an individual user sees on the recommended list. It is the reason why multiple metrics are required to evaluate recommender systems, and a diversity metrics is mainly used for it. In this paper, we compare three different methods for enhancing diversity for personalized recommendation - bin packing, weighted random choice, greedy re-ranking - with a practical e-commerce data acquired from a fashion shopping mall. Besides, we present the difference between experimental results and F1 scores.