• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.10
• /
• pp.2367-2372
• /
• 2015

One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.5
• /
• pp.121-128
• /
• 1997

This paper proposes a class of rearrangeable networks, called generalized rearrangeable networks(GRNs). GRNs are obtained from the Benes network by rearranging the connections between states and the switches within each stage. The GRNs constitute all of the rearrangeable networks which have the recursive decomposition structure and can be routed by the outside-in decomposition of permutations as the Bene network. This paper also presents a necessary condition for a network to be a GRN and a network labeling scheme to check if a network satisfies the condition. the general routing algorithm for the GRNs is given by modifying slightly the looping algorithm of the Benes network.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.11
• /
• pp.2637-2642
• /
• 2015

The low-density parity check(LDPC) code is being widely used due to its outperformed error-correction ability. The decoder of the quasi-cyclic LDPC(QC-LDPC) codes, a kind of LDPC codes, requires a multi-size cyclic shifter(MSCS) performing rotation of various sizes. The MSCS can be implemented with a Benes network, which requires a $3{\times}3$ switch if the number of data to be rotated is a multiple of 3. This paper proposes a control signal generation with lower complexity and a faster $3{\times}3$ switch. For the experiment, the proposed schemes are applied to the MSCS of an IEEE 802.16e WiMAX QC-LDPC code decoder. The result shows that the delay is reduced by about 8.7%.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.16 no.7
• /
• pp.680-695
• /
• 1991

In this paper, the conditions on the number of required copies of a self-routing network with and without extra stages in back-to-back manner are presented respectively for a nonblocking $Multi-Log_2N$ multiconnection network. Actually the obained results hold regardless of connection patterns, i.e., whether a network deploys on-to-one connections or multiconnections. Thus open problems on the nonblocking condition for a multi $Multi-Log_2N$ multiconnection network are solved. Interestingly some of the given formulas comprise the Benes network and the Canto network as a special case repectively. A novel switching system architecture deploying a distributed calls-distribution algorithm is provided to design a nonblocking $Multi-Log_2N$ photonic switching network using a directional coupler. And a directional couplex based call holding demultiplexer is introduced to hold a call until blocking disappears in a switching network and let it enter to a network, provided that the number of switching networks is less than that of required switching networks for a nonblocking $Multi-Log_2N$ network.

• Electronics and Telecommunications Trends
• /
• v.10 no.1 s.35
• /
• pp.113-122
• /
• 1995

현재 발표된 공간 광스위치 구조들은 전자 스위치 및 전자 통신 분야에서 많이 이용된 Clos, Benes, Banyan, omega, shuffle network 등을 directional coupler switch, TIR(total internal reflection) switch, cross X switch 등 여러가지 단위 광스위치를 이용하여 고안한 것으로 서로 다른 장단점을 갖고 있다. 따라서 4 X 4나 8 X 8, 또는 그 이상의 확장된 광스위치를 제작하기 위해서는 이러한 기존 구조에 대한 조사 및 분석이 선행되어야 한다. 본 논문은 현재 개발되어 발표된 광스위치의 구조들을 조사하여 특성을 비교하였다.

• ETRI Journal
• /
• v.39 no.3
• /
• pp.319-325
• /
• 2017

The decoding process of a quasi-cyclic low-density parity check code requires a unique type of rotator. These rotators, called multi-size cyclic-shifters (MSCSs), rotate input data with various sizes, where the size is the amount of data to be rotated. This paper proposes a low-complexity MSCS structure for the case when the sizes have a nontrivial common divisor. By combining the strong points of two previous structures, the proposed structure achieves the smallest area. The experimental results show that the area reduction was more than 14.7% when the proposed structure was applied to IEEE 802.16e as an example.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.118-124
• /
• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.