• The Transactions of the Korea Information Processing Society
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• v.6 no.4
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• pp.959-968
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• 1999

several papers have reported that parallel heuristics or hybrid approaches combining several heuristics can get better results. However, the parallelization and hybridization of any search methods on the single CPU type computer need enormous computation time. that case, we need more elegant combination method. For this purpose, we propose Fast Model of Parallel Heuristics(FMPH). FMPH is based on the island model of parallel genetic algorithms and takes local search to the elite solution obtained form each island(sub group). In this paper we introduce how can we adapt FMPH to the job-shop scheduling problem notorious as the most difficult NP-hard problem and report the excellent results of several famous benchmark problems.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.47-55
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• 1999

In this paper, a new function hazard elimination algorithm is proposed for asynchronous circuit synthesis. In previous approach, function hazard is eliminated by using state graph which is obtained from the state assignment on STG(signal transition graph) representing transition relationship among signals. These algorithms can use conventional hazard removal and synthesis method applied in synchronous system, but it has much computational complexity and takes much time to handle the state graph. Although some hazard elimination algorithm from STG were proposed, it could not reduce the area overhead due to the addition of new signals. The proposed algorithm eliminate function hazard directly on STG and also control the number of minterms and product-term of added signal in order to minimize the area overhead. Experimental results on benchmark data shows that overall circuit area after hazard elimination is decreased about 15% on the average than that of previous method.

• Journal of IKEEE
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• v.12 no.1
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• pp.65-74
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• 2008

One of the popular methods used for pattern classification is the MBR (Memory-Based Reasoning) algorithm. Since it simply computes distances between a test pattern and training patterns or hyperplanes stored in memory, and then assigns the class of the nearest training pattern, it is notorious for memory usage and can't learn additional information from new data. In order to overcome this problem, we propose an incremental learning algorithm (iMPA). iMPA divides the entire pattern space into fixed number partitions, and generates representatives from each partition. Also, due to the fact that it can not learn additional information from new data, we present iMPA which can learn additional information from new data and not require access to the original data, used to train. Proposed methods have been successfully shown to exhibit comparable performance to k-NN with a lot less number of patterns and better result than EACH system which implements the NGE theory using benchmark data sets from UCI Machine Learning Repository.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.7
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• pp.767-773
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• 2014

The carrier-to-noise power ratio is a key parameter for determining the reliability of PVT (Position, Velocity, and Time) solutions which are obtained by a GNSS (Global Navigation Satellite System) receiver. It is also used for locking a tracking loop, deciding the re-acquisition process, and processing advanced navigation in the receiver subsystem. The representative carrier-to-noise power ratio estimation schemes are the narrowband-wideband power ratio method (NW), the MM (Moment Method), and Beaulieu's method (BL). The NW scheme is the most classical one for commercial GNSS receivers. It is often used as an authoritative benchmark for assessing carrier-to-noise power estimation schemes. The MM scheme is the least biased solution among them, and the BL scheme is a simpler scheme than the MM scheme. This paper focuses on the less biased estimation with low complexity when the residual phase noise remains, then proposes a novel carrier-to-noise power ratio estimation scheme with low complexity for GNSS receivers. The asymptotic bias of the proposed scheme is derived and compared with others, and the simulation results demonstrate that the complexity of the proposed scheme is lowest among them, while the estimation performance of the proposed scheme is similar to those of the BL and MM schemes in normal and high gained reception environments.

• Journal of the Korea Society of Computer and Information
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• v.19 no.1
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• pp.149-156
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• 2014

NGE(Nested Generalized Exemplar Method) can increase the performance of the noisy data at the same time, can reduce the size of the model. It is the optimal distance-based classification method using a matching rule. NGE cross or overlap hyperrectangles generated in the learning has been noted to inhibit the factors. In this paper, We propose the DHGen(Dominant Hyperrectangle Generation) algorithm which avoids the overlapping and the crossing between hyperrectangles, uses interval weights for mixed hyperrectangles to be splited based on the mutual information. The DHGen improves the classification performance and reduces the number of hyperrectangles by processing the training set in an incremental manner. The proposed DHGen has been successfully shown to exhibit comparable classification performance to k-NN and better result than EACH system which implements the NGE theory using benchmark data sets from UCI Machine Learning Repository.

• Nuclear Engineering and Technology
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• v.20 no.1
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• pp.27-34
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• 1988

Since the lack of the spent fuel storage capcity has been expected for all Korean nuclear power plants in the mid-1990s, the maximum density rack (MDR) with consolidated fuels can be proposed to overcome the shortage of the storage capacity in KNU 9 & 10 which have most limited capacities. To ensure the safety when the alternatives are applied in the KNU 9 & 10, the multiplication factor are calculated with varying the rack pitch and the thickness of consolidated storage box by the AMPX-KENO IV codes. The computing system is verified by the benchmark calculation with criticality experiments for arrays of consolidated fuel modules, which was reported by B & W in 1981. Also an abnormal condition, i.e. malposition accident, is simulated. The results indicate that the KNU 9 & 10 storage pools with consolidated fuel are safe in the view of the criticality. Thus the storage capacity can be expanded from 9/3 cores into 27/3 cores even with considering equipments and cooling spaces.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.1
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• pp.204-226
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• 2018

Big data processing applications have been migrated into cloud gradually, due to the advantages of cloud computing. Hadoop Distributed File System (HDFS) is one of the fundamental support systems for big data processing on MapReduce-like frameworks, such as Hadoop and Spark. Since HDFS is not aware of the co-location of virtual machines in the cloud, the default scheme of block allocation in HDFS does not fit well in the cloud environments behaving in two aspects: data reliability loss and performance degradation. In this paper, we present a novel location-aware data block allocation strategy (LDBAS). LDBAS jointly optimizes data reliability and performance for upper-layer applications by allocating data blocks according to the locations and different processing capacities of virtual nodes in the cloud. We apply LDBAS to two stages of data allocation of HDFS in the cloud (the initial data allocation and data recovery), and design the corresponding algorithms. Finally, we implement LDBAS into an actual Hadoop cluster and evaluate the performance with the benchmark suite BigDataBench. The experimental results show that LDBAS can guarantee the designed data reliability while reducing the job execution time of the I/O-intensive applications in Hadoop by 8.9% on average and up to 11.2% compared with the original Hadoop in the cloud.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.50-57
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• 2000

We propose a logic synthesis algorithm for the design of FPGAs operating at high speed. FPGA is a novel technology that provides programmability in the field. Because of short turnaround time and low manufacturing cost, FPGA has been noticed as an ideal device for system prototyping. Despite these merits, FPGA has drawbacks, namely low integration and long delay time comparing to ASIC. The proposed algorithm partitions a given circuit into subcircuits utilizing a kernel divisor such that the subcircuits can be performed at the same time, hence reducing the delay of the circuit. Experimental results on the MCNC benchmark show that the proposed algorithm is effective by generating circuits having 19.1% les delay on average, when compared to the FlowMap algorithm.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• Journal of Radiation Protection and Research
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• v.9 no.2
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• pp.97-102
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• 1984

Criticality analyses of the KSC-1(Korean Shipping Cask-1) spent fuel shipping cask have been performed with the help of KENO-IV Monte Carlo computer code and 19-group CSLIB 19 cross section set which was generated from AMPX modular system. The analyses followed a benchmark calculation which has been made regard to the B & W CX-10 criticality facility in order to validate the Monte Carlo code cross section set described above. The KSC-1 shipping cask seems to be safe in the criticality point of view for the transport of one PWR spent fuel assembly under the normal conditions as well as the hypothetical accident conditions.