• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.6-14
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• 2011

This paper presents the design of the battery sensor IC for instrumentation of current, voltage using delta-sigma ADC. The proposed circuit consists of programmable gain instrumentation amplifier (PGIA) and second-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a 0.25 ${\mu}m$ CMOS technology. Design circuit show that the modulator achieves 82 dB signal-to-noise ratio (SNR) over a 2 kHz signal bandwidth with an oversampling ratio (OSR) of 256 and differential nonlinearity (DNL) of ${\pm}$ 0.3 LSB, integral nonlinearity (INL) of ${\pm}$ 0.5 LSB. Power consumption is 4.5 mW.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.8
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• pp.90-97
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• 2014

This paper presents a compensation method of unbalanced phase currents in interleaved bi-directional converters. Phase currents in interleaved bi-directional converter are apt to be unbalanced due to circuit parameter error and switch operation difference. This problem causes the switch element failure and the reduced efficiency of the converter. Therefore, it is necessary that a certain balance control algorithm is provided in interleaved bi-directional converter system. In this paper, a balance control algorithm based on the circular chain control method is proposed. Further, in order to reduce the number of phase current sensors, this paper shows a simple method in which phase currents can be extracted indirectly through a DC-link current sensor in both charging and discharging modes. The validity and the effectiveness of the proposed phase currents balance control algorithm are illustrated through the simulation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.774-784
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• 2009

A wireless sensor network consisting of a large number of nodes with limited battery power should minimize energy consumption at each node to prolong the network lifetime. To improve the sensitivity of wireless sensor networks, an efficient scheduling algorithm and energy management technology for minimizing the energy consumption at each node is desired. ill this paper, we propose energy-aware routing mechanism for maximum lifetime and to optimize the solution quality for sensor network maintenance and to relay node from its adjacent cluster heads according to the node"s residual energy and its distance to the base station. Proposed protocol may minimize the energy consumption at each node, thus prolong the lifetime of the system regardless of where the sink is located outside or inside the cluster. Simulation results of proposed scheme show that our mechanism balances the energy consumption well among all sensor nodes and achieves an obvious improvement on the network lifetime. To verify propriety using NS-2, proposed scheme constructs sensor networks adapt to current model and evaluate consumption of total energy, energy consumption of cluster head, average energy dissipation over varying network areas with HEED and LEACH-C.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.20-27
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• 2011

A CMOS Image Sensor(CIS) mounted on mobile appliances always needs a low power consumption because of the battery life cycle. In this paper, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination, a low power single slope A/D converter with a novel comparator, and etc. Based on 0.13um CMOS process, the chip satisfies QVGA resolution($320{\times}240$ pixels) whose pitch is 2.25um and whose structure is 4-Tr active pixel sensor. From the experimental results, the ADC in the middle of CIS has a 10-b resolution, the operating speed of CIS is 16 frame/s, and the power dissipation is 25mW at 3.3V(Analog)/1.8V(Digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption is reduced approximately by 22% in sleep mode, 20% in operating mode.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.24-25
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• 2013

본 논문은 단일 전류 센서를 이용한 배터리 충방전용 양방향 3상 인터리브드 컨버터의 전류 제어 방법을 제안한다. 기존의 3상 인터리브드 컨버터 전류 제어는 각 상의 인덕터 전류를 센싱해야만 하는 방식이다. 본 논문에서 제안한 전류 제어 방법은 각 상의 인덕터 전류 센싱없이 단일 전류 센싱만으로 인덕터 전류를 제어 할 수 있다. 시뮬레이션을 통하여 본 논문이 제안한 제어 방법의 타당성과 실효성을 증명한다.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.417-418
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• 2013

태양광 발전설비에서 태양광 셀의 출력전력을 최대로 부하에 전달하기 위해 태양광 최대전력추종제어를 한다. 일반적인 태양광 최대전력 추종제어는 태양광 셀의 전압과 전류의 곱인 전력값을 비교하여 최대전력추종제어를 한다. 본 논문에서는 MPPT 컨버터의 출력 파라미터 중 전류만을 센싱하여 태양광 최대전력추종제어를 한다. 또한 태양광 최대 전력추종제어를 통해 최대 출력으로 배터리를 충전하고 허용전류를 초과했을 때에는 전류제어로 충전하도록 설계한다. 이를 통해 Solar Car등과 같은 모터 부하에 적용해 보고자 한다.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.238-239
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• 2012

본 논문에서는 ESS를 위한 3상 인터리브드 양방향 DC-DC 컨버터의 단일 전류센서 기반 상전류 검출 방법을 제안한다. 제안하는 방법은 직류 링크 단에 하나의 전류 센서를 이용하여 전류를 측정하고 스위칭 상태에 따라 각 상의 전류를 복원한다. 따라서 기존의 각 상 전류 센서 이용 시 잠재적으로 내포하고 있는 센서 간 출력특성 불균일 문제에서 자유롭고, 보다 경제적인 시스템 구성이 가능하다. 제안한 방법을 3kW ESS용 컨버터에 적용하여 실험적으로 그 유용성을 검증하였다.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.4
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• pp.83-88
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• 2020

In Solar-powered wireless sensor networks(SP-WSN), the battery is periodically charged, so the best use of harvested energy is more important, rather than minimizing energy consumption. Meanwhile, as is well known, the reliability of communication between sensor nodes is very limited due to the resource-constraint of sensor nodes. In this paper, we propose an advanced FEC (forward error correction) scheme which can give SP-WSN more reliability for communication. Firstly, the proposed scheme uses energy modeling to calculate the amount of surplus energy which can be utilized for extra operations, and then determines the number of additional parity bits according to this amount of surplus energy. At the same time, link quality modeling calculates the optimal parity bits for error recovery in the current data communication environment. Finally, by considering these two parity sizes, it is possible to determine the optimal parity size that can maximize the data reliability without affecting the node black out. Performance verification was performed by comparing the amount of data collected at the sink and the number of outage nodes with other schemes.

• 전자공학회논문지 IE
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• v.47 no.1
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• pp.41-47
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• 2010

It is very important to prolong the lifetime of wireless sensor networks by using their limited energy efficiently, since it is not possible to change or recharge the battery of sensor nodes after deployment. LEACH protocol is a typical routing protocol based on the clustering scheme for the efficient use of limited energy. It is composed of a few clusters, which consist of head nodes and member nodes. Though LEACH starts from the supposition that all nodes have data transferred to a head, there must be some nodes having useless data in actual state. In this paper we propose a power saving scheme by making a member node dormant if previous sensed data and current data is same. We evaluate the performance of the proposed scheme in comparison with original clustering algorithms. Simulation results validate our scheme has better performance in terms of the number of alive nodes as time evolves.

• Journal of IKEEE
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• v.26 no.2
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• pp.299-305
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• 2022

Analog-digital converter (ADC) should be one of the most important blocks that convert various physical signals to digital ones for signal processing in the digital signal domain. As most operations of the analog circuit for sensor signal processing have been replaced by digital circuits, high-resolution performance is required for ADC. In addition, low-power must be the critical issue in order to extend the battery time of mobile system. The existing integrating sigma-delta ADCs has a characteristic of high resolution, but due to its low supply voltage condition and advanced technology, circuit error and corresponding resolution degradation of ADC result from the finite gain of the operational amplifier in the integrator. Buffer compensation technique can be applied to minimize gain errors, but there is a disadvantage of additional power dissipation due to the added buffer. In this paper, incremental signal-delta ADC is proposed with buffer switching scheme to minimize current and igh-pass bias circuit to improve the settling time.