• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.673-676
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• 2008

블루투스와 같은 무선통신의 경우, 베이스밴드에서는 송신단과 수신단의 데이터의 모뎀 인터페이스를 통과한 데이터에 대해 보안성 및 회로의 안정성을 위해 DC 바이어스를 제거해주어야 한다. 송신단에서는 송신할 데이터를 랜덤하게 섞어 에러 정정 모들에 보내주어야 하며 수신단에서는 랜덤하게 평준화된 데이터들을 원래 상태로 복구하여야 한다. 이러한 화이트닝 블록은 필터링을 위한 고유다항식을 목적에 맞게 선택하는 것이 매우 중요하다. 본 논문에서는 하드웨어의 효율성을 높이고 면적을 줄이기 위하여 고유다항식을 $g(D)=D^7+D^4+1$로 선택하여 화이트닝 블록을 설계하였다. 설계한 하드웨어 화이트닝 블록은 Verilog HDL로 기술하고 검증하여 자동 합성방식으로 합성하였다. 합성된 화이트닝 블록은 기준으로 삼는 베이스밴드 마이크로콘트롤러의 동작주파수인 40MHz에서 정상적으로 동작하였다.

• 한국군사과학기술학회지
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• 제22권3호
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• pp.332-340
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• 2019

Electronic warfare systems are needed to be advantageous in the modern war. Many radar threat signals with various frequency spectrums and complicated techniques exist. For detecting the threats, a receiver with wide and narrow-band digital processing is needed. To process a wide-band searching mode, a polyphase filter bank has become the architecture of choice to efficiently detect threats. A polyphase N-path filter aligns the re-sampled time series in each path, and a discrete Fourier transform aligns phase and separates the sub-channel baseband aliases. Multiple threats and CW are detected or rejected when the signals are received in different sub-channels. And also, to process a narrow-band precision mode, a direct down converter is needed to reduce aliasing by using a decimation filter. These digital logics are designed in a FPGA. This paper shows how to design and develop a wide and narrow-band digital receiver that is capable to detect the threats.

• ETRI Journal
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• 제19권3호
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• pp.116-140
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• 1997

The base station transceiver subsystem (BTS) of the CDMA Mobile System is interfaced to mobile stations over the air and to the wired network through a packet switched interconnection network. The potential benefits of CDMA technology are achieved when the transmitter and the receiver are properly designed and implemented. The physical layer of the interface at the base station is implemented with the CDMA ASICs and control circuits in channel card of the BTS. We present the design perspectives and structural illustration of the BTS. Base station modem ASICs and their control to implement the CDMA receiver, Baseband and RF signal processing blocks, and BTS controller are described. Elaborate power control is essential to ensure the high capacity which is one of advantages of the CDMA technology. The closed loop reverse link power control and the forward link power control operated in the BTS are described.

• Journal of information and communication convergence engineering
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• 제17권3호
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• pp.221-226
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• 2019

In this work, a transmitter/receiver front-end module (T/R FEM) with an automatic Tx/Rx switching scheme for a 2.4 GHz microwave power transfer is developed for a retro-reflective beamforming scheme. Recently, research on wireless power transfer techniques has moved to wireless charging systems for mobile devices. Retro-reflective beamforming is a good candidate for tracking the spatial position of a mobile device to be charged. In Tx mode, the T/R FEM generates a minimum of 1 W. It also comprises an amplitude and phase monitoring port for transmitting RF power. In Rx mode, it passes an Rx pilot signal from a mobile device to a digital baseband subsystem to recognize the position of the mobile device. The insertion loss of the Rx signal path is 4.5 dB. The Tx and Rx modes are automatically switched by detecting the Tx input power. This T/R FEM is a design example of T/R FEMs for wireless charging systems based on a retro-reflective beamforming scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권4호
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• pp.293-299
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• 2004

An active RC 2nd order Butterworth filter suitable for a baseband channel-selection filter of a direct conversion receiver is presented. The linearity of the 2nd order Butterworth filter is analyzed. In order to improve the linearity of the filter, the operational amplifiers should have a high linear gain and low 3rd harmonic, and the filter should be designed to have large feedback factor. This second order Butterworth filter achieves-14dBV in-channel (400kHz, 500kHz) IIP3, +29dBV out-channel (10MHz, 20.2MHz) IIP3 and 15.6 $nV/\sqrt{Hz}$ input-referred noise and dissipates 10.8mW from a 2.7-V supply. The analysis and experimental results are in good agreement

• 한국통신학회논문지
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• 제25권9A호
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• pp.1332-1339
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• 2000

본 논문에서는 MCNS(Multimedia Cable N$\xi$twork System)의 DOCSIS(Data Over Cable Service Interface S Specification) 표준안의 물리계층을 지원하는 비대칭형 기저대역 모댐 ASIC 칩의 아키텍쳐와 설계에 대해 기술한다. 구현한 모뎀 칩은 크게 QPSK/16-QAM 방식의 상향 스트림용 송신부와 64/256-QAM 방식의 하향 스트림용 수신부로 구성되어 있으며, 심볼 타이밍 복구회로, 반송파 복구회로. MMA(Multi Modulus Algorithm)와 LMS(Least Mean Square) 알고리즘을 적용한 결정 궤환 구조의 블라인드 등화기를 포함한다. 구현한 모뎀 칩은 64/256-QAM 변복조 방식에서 각각 48Mbps, 64Mbps의 데이터 전송률을 지원하고, 심볼 전송률은 기존의 QAM 수신기들보다 빠른 8MBaud를 갖는다. 구현한 칩은 $0.35\mu\textrm{m}$ 표준 셀(Standard Cell) 라이브러리를 사용하여 논리합성을 수행하였으며, 총 게이트 수는 약 29만 게이트이며, 현재 ASIC 칩으후 제작중이다.

• The Journal of the Acoustical Society of Korea
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• 제21권1E호
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• pp.18-24
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• 2002

This paper discusses the development of an acoustic vector channel simulator for the performance analysis of an acoustic digital communication system. The channel simulator consists of transmission module, acoustic channel model, receiver, beamformer, and adaptive equalizer. The source signal (QPSK) is generated by the specified parameters. The transmitted signal generates multipath signals which have a different delay, amplitude and doppler frequency. The paper presents in details the approach to the performance analysis of an acoustic digital communication system according to the antenna structure and the various baseband signal processing techniques.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.305-308
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• 2001

In this paper, we realized a transceiver system for short distance communication with a commercial RF module working in ISM band and a microprocessor. Also we measured system performance by transmitting baseband data in a building and then we compared the demodulated 긴ta bits with stored data bits in a PC connected with demodulator. The RF module in the experiments works oかy in the bandwidth, 424MHz - 429MHz. with FM mode. The signal level degrades as the distance between transmitter and receiver increases we measured the signal level and bit error in the building of engineering college of our university. we present the measured data with various locations in the building. and the data may be used in design short distance network in a building.

• 융합신호처리학회논문지
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• 제5권4호
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• pp.333-337
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• 2004

본 논문은 IEEE 802.11a 무선 LAN 규격을 OFDM을 적용한 5GHz 기저 대역의 송 수신부 모뎀을 설계하고 FPGA로 실현하였다. 고속 데이터 전송시 발생하는 심벌간 간섭(ISI)을 제거하기 위하여 Normalized LMS 알고리듬을 적용한 단일탬 등화기를 사용하여 제거하였고, 또한 반송파 주파수 옵셋 알고리듬을 이용하여 채널간 간섭(ICI)을 제거하였다. 송ㆍ수신기간의 전송은 에러없이 정확히 전송되어짐을 시뮬레이션을 통하여 입증하였으며, 또한 타이밍 시뮬레이션 결과 최대 동작주파수는 20.3MHz로 IEEE 802.11a 무선 LAN 방식의 동작속도를 만족하였다. 그리고 설계시 DSP와 EMB(Embedded Memory Block)블록을 사용하여 레지스터의 수를 상당히 줄일 수 있었다. 모뎀 설계는 VHDL를 이용하여 설계하고 Altera사의 Stratix EPIS25FC672 FPGA Chip을 사용하여 구현하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.289-291
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• 2007

The Digital Multimedia Broadcasting(DMB) system is developed to offer high quality audio-visual multimedia contents to the uses by the various portable terminals in the mobile environment. Integrated complex reception platform is required to receive multimedia broadcasting services transmitted from various transmission media. In this paper, we present the design and implementation technic for providing the both of terrestrial and satellite DMB services simultaneously using the same hardware platform. The implemented complex receiving terminal to accommodate these DMB services simultaneously need composed of it RF module. it baseband module, it complex control module and the complex de-multiplexer module. The complex control module is designed using uClinux operating system. The complex de-multiplexer, which perform the functions of the address decoder and each DMB stream de-multiplexer, is implemented. with FPGA device. The implemented platform is tested in a real environment and its performance is satisfied with required performance criteria.